Lab 05 – EE 421L

Authored by Chandon Esplin,

EsplinC2@UNLV.Nevada.edu

10/05/2016 

Design, layout, and simulation of a CMOS inverter

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Pre-Lab Tasks

• Back-up all of your work from the lab and the course.
• Go through Tutorial 3 seen here

Design, layout, and simulation of a CMOS inverter

Experiment(s):

• Draft schematics, layouts, and symbols for two inverters having sizes of: 
• 12u/6u (= width of the PMOS / width of the NMOS with both devices having minimum lengths of 0.6u)
• 48u/24u where the devices use a multiplier, M = 4 (set along with the width and length of the MOSFET, image)
• Example layouts can be found here.
• Notice that power is run on the top of the cell via metal1 and ground is run on the bottom of the cell also via metal1
• Power (vdd!) is connected to the n-well using the ntap cell 
• Ground (gnd!) is connected to the p-substrate using the ptap cell
• Running power and ground with a single row of contacts, instead of 2 as seen below, is fine to reduce layout size
• Your schematics should have two pins, e.g., A and Ai
• Your layouts should have 4 pins: A, Ai, vdd!, and gnd! (note how lowercase letters are used for power and ground)
• Your lab reports should document your efforts and results including showing that the extracted layouts and schematics LVS correctly
• Zip up these cells in a directory call lab5_rjb.zip (last two or three letters are your initials) and link to your lab report

Results:

Draft schematics, layouts, and symbols for two inverters having sizes of: 12u/6u (= width of the PMOS / width of the NMOS with both devices having minimum lengths of 0.6u)

12μ/6μ by 0.6μ Inverter Schematic & Symbol

12μ/6μ by 0.6μ Inverter Layout

12μ/6μ by 0.6μ Inverter DRC & LVS

48μ/24μ by 0.6μ (m=4) Inverter Schematic & Symbol

48μ/24μ by 0.6μ (m=4) Inverter Layout

48μ/24μ by 0.6μ (m=4) Inverter LVS & DRC

Design Directory Found here lab5_CJE.zip

Using SPICE simulate the operation of both of your inverters showing each driving a 100 fF, 1 pF, 10 pF, and 100 pF capacitive load

o Use UltraSim (Cadence's fast SPICE simulator for larger circuits at the cost of accuracy) and repeat the above simulations

12μ/6μ by 0.6μ Inverter Simulation Schematic

12μ/6μ by 0.6μ Inverter Simulation Results

12μ/6μ by 0.6μ Inverter Simulation Results (UltraSIM)

48μ/24μ by 0.6μ (m=4) Inverter Simulation Schematic

48μ/24μ by 0.6μ (m=4) Inverter Simulation Results

48μ/24μ by 0.6μ (m=4) Inverter Simulation Results (UltraSIM)

Discussion:

Comment, in your report, on the results

Results of Driving Capacitive Loads as Capacitor Increases in Size

The connection of an inverter to a capacitor provides a glimpse into the fundamental operation of capacitors. Storing energy in the electric field between its’ two plates, the capacitor expels that stored energy, as the inverter drops the voltage to a lower value relative to the capacitor. As viewed in both inverter circuit simulations, the larger the capacitor connected i.e. the more energy stored within, the less drop in voltage as seen by output Ai.

Design Directory Found here lab5_CJE.zip

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