Lab 7 - EE 421L
4-bit Inverter Schematic | 4-bit Inverter Symbol |
Schematic used to simulate the 4-bit Inverter under different capacitive loads | Simulation Plots of the 4-bit Inverter |
NOR Gate Schematic | NOR Gate Symbol |
NAND Gate Schematic | NAND Gate Symbol |
NOT Gate Schematic | NOT Gate Symbol |
AND Gate Schematic | AND Gate Symbol |
OR Gate Schematic | OR Gate Symbol |
No Load | 100 fF Load |
500 fF Load | 1 pF Load |
MUX Schematic | MUX Symbol |
MUX Simulation Schematic | Simulation Results |
MUX Schematic (With an Inverter) | Symbol |
Simulation Schematic | Simulation Results |
8-bit MUX/DEMUX Schematic |
8-bit MUX/DEMUX Simulation Schematic |
Simulation Results |
Full Adder Schematic | Full Adder Symbol |
Full Adder Simulation Schematic | Simulation Results |
Full Adder Layout | Extracted Layout |
DRC | LVS |
8-bit Full Adder Schematic | 8-bit Full Adder Symbol |
8-bit Full Adder Layout | Extracted Layout |
DRC | LVS |
8-bit Full Adder Schematic | 8-bit Full Adder Simulation Schematic (Carry-in/Carry-out) |