Lab

Lab 7 - EE 421L

Authored by Ulises Diaz Jr.

Date: 11/15/16

Pre-lab:

I backed up all of my work from lab 6 and the course.
I finished going through Tutorial 5.

Lab:

Part 1 (Tutorial 5/Ring Oscillator): The first part of this lab was going over Tutorial 5 from the CMOSedu website. Basically, the tutorial went over how to use buses and arrays to create a schematic and layout of a ring oscillator. Below are the images for the schematic, symbol, and layout of the ring oscillator:

Inverter Schematic (Using Buses) Inverter Symbol

Inverter Layout

Extracted Layout

DRC showing no errors

LVS showing the netlists matched

Inverter simulation

Part 2 (4-bit Inverter): After going over the tutorial, I then created the 4-bit inverter using buses and arrays as learned from Tutorial 5. Once the 4-bit inverter was created, I then simulated the results under different capacitive loads.

4-bit Inverter Schematic	4-bit Inverter Symbol
Schematic used to simulate the 4-bit Inverter under different capacitive loads	Simulation Plots of the 4-bit Inverter

4-Bit Inverter Simulation Results: Based on this simulation of the 4-bit inverter, it is evident that the capacitive loads definitely create a delay for the output of the inverter. By comparing the 100 fF (out <3>) load with the 1 pF (out<1>) load, it is obvious that the higher the load, the larger the delay of the output pulse due to a higher time it takes to charge a larger capacitor.

Part 3 (Schematics and Simulations of 8-bit Logic Gates): The next part of the lab involved using buses and arrays to create and simulate the following 8-bit Logic Gates: NOT, NAND, NOR, AND, OR. The following table shows the schematics and symbols of the logic gates:

NOR Gate Schematic	NOR Gate Symbol
NAND Gate Schematic	NAND Gate Symbol
NOT Gate Schematic	NOT Gate Symbol
AND Gate Schematic	AND Gate Symbol
OR Gate Schematic	OR Gate Symbol

Next, the following images show the schematic of simulating all the logic gates, and the results as well. The loads of the gates are varying capacitive loads while the inputs are pulses.

Table Showing Simulations:

No Load	100 fF Load
500 fF Load	1 pF Load

Logic Gates Simulation Results: As with the 4-bit inverter, it is still apparent that increasing the capacitive loads of the gates will definitely add delays for the outputs of the gates. For example, based on the simulation from the no load plots compared to the 1 pF plots, you can see there is no delay with no load and there is a delay with a 1 pF load.

Part 4 (Schematic and Simulation of a MUX/DEMUX Logic Device): For the next part of the lab, I created the schematic for a Multiplexer or MUX logic device. Basically, a MUX works like a switch or selector. Depending on the control signal of the MUX, the output signal is a "1" or "0" based on what state the selector of the MUX is in. For example, if the control signal is "1", then the MUX will select "1" for the output. For this part of the lab, the MUX is a 2-1 MUX. Additionally, for the MUX to operate as a DEMUX, you basically change the outputs of the MUX to the inputs of the DEMUX and you change the inputs of the MUX to the outputs of the DEMUX.

The schematic and simulation of the MUX is shown below:

MUX Schematic	MUX Symbol
MUX Simulation Schematic	Simulation Results

Next, we can invert the inputs and outputs of the MUX to get the same results:

MUX Schematic (With an Inverter)	Symbol
Simulation Schematic	Simulation Results

Now, using buses and arrays I created an 8-bit MUX/DEMUX circuit and below are the images and results of the simulation:

8-bit MUX/DEMUX Schematic

8-bit MUX/DEMUX Simulation Schematic

Simulation Results

Part 5(Full Adder/8-bit Full Adder): The last part of this was the most challenging part. I created a full-adder circuit from the CMOS book, then I created the layout for the full adder circuit. A lot of pain was felt in making this layout, but eventually it DRC'd and LVS'd after many hours of work. Below are the images for the schematic and the symbol of the full adder:

Full Adder Schematic

Full Adder Symbol

Next, I tested the schematic for the full adder by using the symbol and pulses as the input. From the simulation results, the full adder was working properly. For example, when the A, B, and C inputs are "1", the outputs S and Cout also equal "1". Here are the images:

Full Adder Simulation Schematic

Simulation Results

After successfully simulating the full adder, the fun part came next. Below are the images of the layout of the full adder, as well as the DRC and LVS results:

Full Adder Layout	Extracted Layout
DRC	LVS

Furthermore, after creating the layout the next step was to create an 8-bit full adder. Of course, the schematic for the 8-bit adder will again use buses and arrays to make a concise schematic overall. Below are the images:

8-bit Full Adder Schematic

8-bit Full Adder Symbol

The layout of the 8-bit inverter was not that bad because all I had to do was simply copy the full adder layout 8 times and change some connections. All I had to change was to connect the carry-in to the carry-out of the adders, and change the An, Bn, and Cn pins to 8-bit inputs. Below is the layout passing DRC and LVS:

8-bit Full Adder Layout	Extracted Layout
DRC	LVS

Finally, the very last step of this lab was to simulate the operation of the 8-bit Full Adder. Basically, I used the following truth table to test the 8-bit Full Adder based on the output waveforms:

8-bit Full Adder Schematic	8-bit Full Adder Simulation Schematic (Carry-in/Carry-out)

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