Lab

Lab 5 - EE 421L

Authored by Ulises Diaz Jr.

Date: 10/5/16

Pre-lab:

I backed up all of my work from lab 4 and the course.
I finished going through Tutorial 3.
As stated before, all the NMOS devices in this lab have their body connected to ground, and all the PMOS devices should have their body connected to VDD (5V).

Lab:

The purpose of this lab was to gain more practice with Cadence, and be able to create a schematic, symbol, and layout for two different inverters by going through Tutorial 3. Basically, an inverter (also called NOT gate) is a digital logic device that inverts the logic from the input for its output. For example, if a logic signal "1", or HIGH is assigned as the input of the inverter, the output will give "0", or LOW. The first inverter will have a PMOS with W/L of 12u/0.6u, and an NMOS of 6u/0.6u. The second inverter will also have a PMOS and NMOS with the same W/L, but the PMOS and NMOS will have a multiplier of m=4. After creating the schematics and layouts for the two inverters, I will simulate them under varying capacitive loads, and discuss the results. Lastly, the end of this report will include a zip folder named lab5_ud.zip showing all the files and pictures for this lab.

Part 1 (Schematics and Symbols):

First, I will discuss the schematic and layout for the first inverter with a PMOS with W/L of 12u/0.6u, and an NMOS of 6u/0.6u. The image below shows the schematic of the inverter using a PMOS and NMOS:

Basically, A is the original logic input and Ai will be the inverted logic input.

After saving and checking the inverter schematic, I created a symbol to simplify the simulation process later. The symbol is shown below:

For the second inverter, the schematic is very similar, but the difference is that the PMOS and NMOS devices are 4 times larger. The schematic and symbol for the second inverter are shown below:

Note: For this inverter, all I had to do was change the multiplier, or the m parameter, to 4. This multiplies both the width and length of the PMOS and NMOS by 4 to obtain a W/L of 48u/24u.

Part 2 (Layouts and Simulations):

After creating the schematic and symbol for the inverters, the next step for this lab was to layout both inverters and simulate them. The table below shows the layouts and extracted layouts of both inverters, as well as the DRC and LVS results:

Table 1

Layout of the first inverter	Extracted Layout	DRC and LVS
Layout of the second inverter	Extracted Layout	DRC and LVS

After creating the layouts for both inverters, the last part of this lab was to simulate the inverters under different capacitive loads (100fF, 1pF, 10pF, and 100pF). In my schematics, I left the load capacitor in terms of a variable for simulation purposes. To simplify the amount of figures used for the simulations, I simulated both inverters under a transient response using parametric analysis sweeping the output of different capacitive loads. Additionally, the lab required the use of UltraSim as a simulator, and then compare the results of the simulations using Spectre and UltraSim. The Table below shows my schematics I used for the simulations as well as the results:

Table 2

First Inverter Simulation Schematic	Simulation Results (Spectre)	Simulation Results (UltraSim)
Second Inverter Simulation Schematic	Simulation Results (Spectre)	Simulation Results (UltraSim)

NOTE: The Parametric Analysis sweeps the output capacitor (with variable c) under different values in the simulation.

Results: The simulations of both inverters were easy to analyze. For example, for the first inverter when the capacitive load is low (i.e. 100fF or 1 pF), the capacitor charges quickly and outputs the inverted input without much delay. However, as you increase the capacitance (i.e. 10 pF or 100 pF), the capacitor becomes slower to charge, therefore it can't charge as quickly since the input pulse is too fast. Consequently, the output is not inverted entirely. Additionally, for the second inverter with bigger width and longer length shows slightly different results. For example, under a 1 pF load, the input signal has to travel for a little longer distance through the MOSFETs, and the inverted output in a way experiences some sort of delay because of the time it takes to charge the capacitor.

Furthermore, the simulation results using Spectre and UltraSim were not so different. They were very similar, but it Spectre took a little longer to simulate, but gave better results. UltraSim was faster to simulate, but it was slightly less accurate in the waveforms.

This is the end of my lab report.

This is my zip-folder for this lab:

lab5_ud.zip

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