Lab 3 - ECE 421L 

Authored by Dominique Anguiano,

Email: anguian3@unlv.nevada.edu

September 15, 2016

The zip file for this lab can be downloaded here.

 Pre-lab duties for this weeks lab required us to back-up all of our work and to finish Tutorial 1.  This tutorial had us layout a 10k resistor in order to become more familiar with the software as well as to help us be more efficient in this week's lab due to the fact that a 10k resistor is being used in the main portion of the lab.

Since we know that the resistance of an n-well resistor is 

    R = Rsquare * L/W

and we only only have control over the length and width of this rectangle, we must modify this ratio to achieve our desired resistance of 10k Ohms.  We also know that the sheet resistance is approximately equal to 800 Ohms in the C5 process and if we set W to be 4.5 microns we can ensure that the width falls on the 0.15 micron grid, all we have to do is solve for the length of the rectangle.

So we have,

    10k = 800 * L/4.5

=> L = 56.25

This is the value of L that would satisfy having a 10k resistor.  However if we are going to use these values for a Layout, a few additional steps must be followed.

Now that we have a value for L, we can divide it by 2 in order to determine the positions of the Left and Right edges.

    56.25/2 = 28.125

Once we have this value, we must now check if this value will fall on the 0.15 micron grid, so we divide the value by 0.15.

    28.125/0.15 = 187.5

Because this value is not a whole number, it will not fall on the 0.15 micron grid, therefore we must slightly change the dimensions of the rectangle so that the edges will fall on the grid.  For our 10k n-well resistor, a total length of 56.1 satisfies these requirements.  Below is an image from Cadence showing these values being used in the dimensions of a 10k n-well resistor.

The length of this resistor can also be measure by using ruler tool which is access by pressing the 'k' key.  Once this tool is selected, the user can simply click on one corner of the resistor and drag the ruler over to another corner to see the distance between those two points.

DAC Layout

    The DAC layout is made by creating a layout of a 2R resistor in parallel with an R resistor.  This is seen below where the top two resistors are the 2R resistor and the bottom resistor is the R resistor.  This 1-bit of the DAC is connected to the next bit by connecting the metal1 layer, which is heading towards the top, to the bottom resistor of the next section, the section looks identical to what is seen on the bottom right corner of the image.

 This continues until ten inputs are created. The input in the above image is marked by b0.  The completed DAC can be seen below.

The layout of the DAC seen above passes both the DRC and the LVS.

Simulations

With both the LVS and DRC passed all that is left to do is to simulate the DAC to ensure it functions as expected.

In order to simulate the layout, we can copy the simulation cell from last weeks lab and open up the spectre state.

 Then in the ADE, you can follow the menu shown below to enter the environment options. 

  In these options the text "extracted" can be added to the area highlighted below.

 Once this is done, the window can be exited by pressing "OK".  Now all that is left is to press the green arrow in the ADE and the simulation will run.

 As we can see from the simulation results above, the DAC works as expected.

 The above steps can be repeated with the delay simulation from lab 2 in order to simulate the layout's delay as well.

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