EE 421L Digital Electronics Lab #4

Authored by Jonathan Young on September 28, 2015
Email: youngj1ATunlv.nevada.edu

Lab Description:

The purpose of this lab is to show the IV (current vs. voltage) characteristics and layout of NMOS and PMOS devices in ON's C5 process.

Pre-Lab:

1. Back-up all of your work from the lab and the course.
2. Read through this lab before starting it.
3. Go through Tutorial 2.
4. In the simulations in this lab the body of all NMOS devices (the substrate) should be at ground (gnd!) and the body of all PMOS devices (the n-well) should be at a vdd! of 5V.

Creating the NMOS (From Tutorial 2):

The following images were generated while following Tutorial 2 to demonstrate going through the tutorial process. This tutorial information is heavily used within the lab, as the construction of the NMOS and PMOS transistors will be used. In this scenario, a three terminal NMOS schematic was used. Later on, it was switched to a four terminal NMOS schematic due to LVS not being able to compare as it is expecting a four terminal device and not a three terminal device.

Image showing NMOS in schematic
Figure 1: This image shows the instantiation of the NMOS transistor in a schematic layout.
Creation of NMOs symbol
Figure 2: This image shows the creation of a NMOS transistor symbol to be used in simulation schematics.
Schematic of NMOS for Simulation
Figure 3: This image uses the preceding Figure symbol to create a schematic showing the IV characteristics.
Setting up the NMOS model for Simulation
Figure 4: This image shows how to addition of the NMOS model to simulations, which are required otherwise the NMOS schematic will not simulate. Note: This model is for the ami06 process.
DC Simlation setup
Figure 5: This image shows the analysis setup to start simulations.
Parasitic Analysis Setup Window
Figure 6: This image shows the parasitic analysis setup to allow VGS to change in steps.
Simulation Setup Window
Figure 7: This image shows the simulation window setup.
NMOS Simulation
Figure 8: This image is the result of the setup simulations above, showing the IV characteristics.
NMOS Layout 3 Terminal
Figure 9: This image shows the corresponding layout of a NMOS, using the provided layout of an NMOS and PTAP from Cadence.
NMOS Extracted Layout 3 Terminal
Figure 10: This image shows the extracted layout, showing the NMOS as a symbol we are used to seeing as well as its size.
NMOS LVS Error
Figure 11: This image shows that LVS failed because the device that is expected is a 4-terminal device and not a 3-terminal device as shown above. Thus, the layout must be modified to show the 4th-terminal even though it is connected to ground.
Corrected NMOS Schematic
Figure 12: This image shows the NMOS device as a 4-terminal device, thus correcting the LVS problem in the previous figure. Note: This pin (B) is connected directly to ground.
NMOS Extracted Layout without LVS Errors
Figure 13: This image shows the LVS occurred without errors and that the layout and schematic match. This has corrected the problem seen in the previous two figures.
NMOS Extracted Simulation
Figure 14: This image shows the extracted layout simulation of the IV characteristics of the NMOS transistor.

Creating the PMOS (from Tutorial 2):

The following images were generated while following Tutorial 2 to demonstrate going through the tutorial process. This tutorial information is heavily used within the lab, as the construction of the NMOS and PMOS transistors will be used.

Schematic of a 4 Terminal PMOS
Figure 15: This image shows a four-terminal PMOS in schematic form.
Symbol of a 4 Terminal PMOS
Figure 16: This image shows the symbol for the PMOS device in the previous figure.
Schematic of PMOS used for Simulations
Figure 17: This image is the PMOS in schematic form, which is used for simulations.
PMOS Simulation Setup Window
Figure 18: This image shows the simulation setup window for the PMOS, including the parasitic analysis setup.
Layout of PMOS from Schematic
Figure 19: This image shows the PMOS layout of the schematic in Figure 15.
Simulation of PMOS Schematic
Figure 20: This image shows the simulations of the PMOS using the schematic.
Simulation of PMOS using the Extracted Layout
Figure 21: This image shows the simulation of the PMOS using the Extracted layout.

Post-Lab:

1. Generate 4 schematics and simulations (see the examples in the Ch6_IC61 library, but note that for the PMOS body should be at vdd! instead of gnd!):
1a. A schematic for simulating ID v. VDS of an NMOS device for VGS varying from 0 to 5 V in 1 V steps while VDS varies from 0 to 5 V in 1 mV steps. Use a 6u/600n width-to-length ratio.
1b. A schematic for simulating ID v. VGS of an NMOS device for VDS = 100 mV where VGS varies from 0 to 2 V in 1 mV steps. Again use a 6u/600n width-to-length ratio.
1c. A schematic for simulating ID v. VSD (note VSD not VDS) of a PMOS device for VSG (not VGS) varying from 0 to 5 V in 1 V steps while VSD varies from 0 to 5 V in 1 mV steps. Use a 12u/600n width-to-length ratio.
1d. A schematic for simulating ID v. VSG of a PMOS device for VSD = 100 mV where VSG varies from 0 to 2 V in 1 mV steps. Again, use a 12u/600n width-to-length ratio.
2. Lay out a 6u/0.6u NMOS device and connect all 4 MOSFET terminals to probe pads (which can be considerably smaller than bond pads [see MOSIS design rules] and directly adjacent to the MOSFET (so the layout is relative small).
2a. Show your layout passes DRCs.
2b. Make a corresponding schematic so you can LVS your layout.
3. Lay out a 12u/0.6u PMOS device and connect all 4 MOSFET terminals to probe pads.
3a. Show your layout passes DRCs.
3b. Make a corresponding schematic so you can LVS your layout.

Schematics and Simulations:

This section covers the schematics and simulations of the NMOS and PMOs devices to produce IV characteristics. This is done to meet requirement 1 (a-d).

NMOS Simulation Schematic
Figure 22: This schematic was drafted using the NMOS4 transistor. The body of the device is connected to ground. The VGS will be set as a variable for parametric analysis, and VDS (vdc) is set to 0V, as it will be swept from 0V to 5V in 1 mV increments.
Simulation of NMOS Schematic
Figure 23: This image is the simulation of the circuit, showing ID against VDS. The purple is when VGS is at 5V and the red is when VGS is 0V. Thus, each curve represents a step up in current to VGS.
NMOS Simulation Schematic
Figure 24: This image is the schematic of the circuit for requirement 2. The body of the circuit is connected to ground. VDS (vdc) is set to be 100mV and VGS will be swept from 0V to 5V in 1mV increments.
Simulation of NMOS Schematic
Figure 25: This image shows the simulation result of Figure 24. The reason for VGS behaving this way is to show how the gate acts as an electronic value, thus allowing current to flow when electromotive force is applied.
PMOS Simulation Schematic
Figure 26: This image is the schematic of the circuit for requirement 3, the PMOS. The body of the circuit is connected to VDD (5V).
Simulation of PMOS Schematic
Figure 27: This image shows the simulation of the circuit in Figure 26. The current is flowing through the drain and is negative since the current is being measured from the drain. This is correct, showing the same result as the previous NMOS simulation if inverted.
PMOS Simulation Schematic
Figure 28: This image is the schematic of the circuit for requirement 2, the PMOS. The body of the circuit is connected to VDD (5V). VSG is swept from 0V to 2V in 1mV increments.
Simulation of PMOS Schematic
Figure 29: This image is the simulation of the circuit in Figure 28 and shows how the gate acts as an electronic valve as VSG increases. As VSG increases, more flow of electric current is allowed.

NMOS Layout (6u/0.6u) using Probe Pads:

The probe pads used below were provided in the lab direction's page, which can be found by clicking here.

Schematic of NMOS with probe pads
Figure 30: This image is the schematic of the NMOS with four probe pads connected to each input terminal.
Layout of NMOS with probe pads with no DRC errors
Figure 31: This image shows the layout of the schematic in Figure 30, including the probe pads. It also shows that it DRCed without errors.
Close-up of NMOS Laypout
Figure 32: This image is a close-up view of the image in Figure 31, showing the NMOS as well as its size.
Extracted Layout of NMOS with probe pads with no LVS errors
Figure 33: This image shows the extracted layout of Figure 31. It also shows that the LVS did not encounter any errors and that the layout matches the schematic (netlists).
Close-up of NMOS Extracted Laypout
Figure 34: This image is a close-up of the extracted layout seen in Figure 33. Note: It shows the dimensions of the NMOS.

PMOS Layout (12u/0.6u) using Probe Pads:

The probe pads used below were provided in the lab direction's page, which can be found by clicking here.

Schematic of PMOS with probe pads
Figure 35: This image is the schematic of the PMOS with four probe pads connected to each input terminal.
Layout of PMOS with probe pads with no DRC errors
Figure 36: This image shows the layout of the schematic in Figure 35, including the probe pads. It also shows that it DRCed without errors.
Close-up of PMOS Laypout
Figure 37: This image is a close-up view of the image in Figure 36, showing the PMOS as well as its size.
Extracted Layout of PMOS with probe pads with no LVS errors
Figure 38: This image shows the extracted layout of Figure 36. It also shows that the LVS did not encounter any errors and that the layout matches the schematic (netlists).
Close-up of PMOS Extracted Laypout
Figure 39: This image is a close-up of the extracted layout seen in Figure 38. Note: It shows the dimensions of the PMOS.

Cadence Back-up:

The lab directory, containing the layouts, schematics, simulations, and symbols from above can be download here. This link is provided for informational and grading purposes only. All other use is prohibited.