Lab 8 - EE 421L
Authored by
Kirk Vrigian
Youssef Abdallah
Saied Samara
Brandon Thomas
11/25/15
vrigiank@unlv.nevada.edu
Lab Description:
- Students
will lay out a set of test structures on a chip for manufacture.
Lab Requirements:
Your chip should include the following test structures:
- One up/down counter with clear
- The outputs of your counter should be buffered before connecting to a pad
- A 31-stage ring oscillator with a buffer for driving a 20 pF off-chip load
- NAND and NOR gates using 6/0.6 NMOSs and PMOSs
- An inverter made with a 6/0.6 NMOS and a 12/0.6 PMOS
- Transistors,
both PMOS and NMOS, measuring 6u/0.6u where all 4 terminals of each
device are connected to bond pads (7 pads + common gnd pad)
- Note
that only one pad is need for the common gnd pad. This pad is used to
ground the p-substrate and provide ground to each test circuit
- Using
the 25k resistor laid out below and a 10k resistor implement a voltage
divider (need only 1 more pad above the ones used for the 25k
resistor)
- A 25k resistor implemented using the n-well (connect between 2 pads but we also need a common gnd pad)
- Whatever else you would like to fabricate to use the remaining pins on the chip
- Feel free to "sign" the chip or add a graphic (see the bottom of this webpage). Copy the final, DRC and LVS clean cell you want to fabricate, and then add the graphic since the graphic won't DRC
- Also
note that you can reduce the number of pins needed by sharing some
of them (two resistors, for example, only need 3 pins)
Experimental Results:
Ring Oscillator:
As
seen above, the oscillator is powered by pin 39 with an output on pin 40.
The oscillator will break away to the counter, but this will be
discussed elsewhere. To be able to measure the ring oscillator, a
buffer has been added internally in the chip. This buffer should be
enough to drive the ~20 pF capacitance of the scope probe. In every
instance, we must connect pin 20 to ground, and pin 39 to vdd.
Mesuring the Ring Oscillator Frequency:
Connect pin 20 to ground.
Connect pin 39 to vdd.
Connect a jumper from pin 39 to VDD PIN
Using a scope probe, connect to the output of the ring oscillator on pin 40.
Using the oscilloscope, measure the time it takes for one period to occur.
Find the measured frequency of the device by the following formula: F = 1/T where T is the time for a single period.
NMOS/PMOS:
Connect power to VDD PIN.
The
body of the NMOS is tied to ground. This means the global ground (pin 20) must be
connected to ground.
Testing the NMOS and PMOS:
The drain of the NMOS is connected to pin 30.
The source is connected to pin 29
The body of the NMOS is connected to gnd or pin 20.
The gate of the NMOS is connected to pin 31.
The source of the PMOS is connected to pin 34.
The gate of the PMOS is connected to pin 33.
The drain of the PMOS is connected to pin 32
The body of the PMOS is connected to pin 35.
Resistor/Divider:
As
seen in the schematic, the resistor divider is connected to pins 37 and 38 of
the chip. To make sure that the PN junction between the N-Well of the
resistors, and the P-Substrate of the bulk is reverse biased, apply
ground to pin 20.
In order to measure the 25kOhm resistor:
Connect pin 20 to ground.
Using a multimeter, place one lead on pin 38 and the other on pin 37.
To measure the 10kOhm resistor:
Connect pin 20 to ground.
Using a multimeter, place one lead on pin 38 and the other on pin 20.
Voltage Divider:
Connect pin 20 to ground.
Using a DC power supply, connect +5V to pin 37.
Connect a jumper from pin 37 to VDD PIN.
Using a multimeter, place one lead on pin 37 and the other on pin 20.
With the notion of a voltage divider, we should see around +1.4V at on pin 37.
Logic Gates:
Inverter
The inverter utilizes pins 13, 14, 15 and 20.
Supply the power to the logic gate
Power goes to pin 15 and ground goes to pin 20
Connect a jumper from pin 15 to VDD PIN.
Input of the inverter is pin 13, the output is pin 14.
NAND Gate:
The NAND gate utilizes pins 21, 22, 23, 24 and 20.
Supply the power to the logic gate
Power goes to pin 21 and ground goes to pin 20
Connect a jumper from pin 21 to VDD PIN.
Input A of the NAND gate is pin 22.
Input B of the NAND gate is pin 23.
AnandB (output) is pin 24.
NOR Gate:
The NOR gate utilizes pins 25, 26, 27, 28 and 20.
Supply the power to the logic gate
Power goes to pin 25 and ground goes to pin 20
Connect a jumper from pin 25 to VDD PIN.
Input A of the NOR gate is pin 26.
Input B of the NOR gate is pin 27.
AnorB (output) is pin 28.
8-bit Up/Down Counter:
Pins 1-8
are the outputs, pins are the load inputs, up/down is on pin , Note that VDD for
the counter is pin VDD PIN (global VDD).
Up/down counting
The
clear pin has to be a logic high for the counter to count up
or down. A logic “1” on the up/down pin will make the counter count up
while a logic “0” will make the counter count down. We have a
asynchronous clear meaning that whenever the clear pin goes low,
regardless of the clock edge, the output of the counter will go to
zero.
All of the files for this lab can be found here.
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