Lab 7 - EE 421L 

Authored by Luis A. Soriano,

Email: sorian20@unlv.nevada.edu

Date: November 3, 2015

Prelab - Turorial 5: Design, layout and simulation of a ring oscillator

In this prelab, we have to go through Tutorial 5, so we start by copying Tutorial_4 into a new library called Tutorial_5.
In here, we created the schematic of a ring oscillator using 31 inverters connected in series.
   

   
Since this schematic looks too long, we draft a short and nicer version using buses.
 

   
'Check and Save' to show no errors were encountered.

   
Then, we can simulate the oscillator.

   
The ring oscillator is now laid out.
   

 

 
DRC the layout to verify that any rule was violated.

   
The output 'osc_out' is on metal2 layer, meanwhile vdd and gnd are on metal1 layer. The extracted layout is shown below.
   

   
LVS (layout vs schematic) can now be performed.

 
It is seen that both netlists match!
Now, a symbol for the ring oscillator is created.

   
A schematic is drafted to simulate the above symbol.

 
The simulation is performed ove a range of 200ns
 

   
The plot is the same as the previous simulation, as expected.
This ends the prelab.
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Post Lab- Word inverters, muxes, and high speed adders using buses and arrays
In this lab experiment we were to design and simulate arrays  of inverters, NAND, NOR, AND, OR, 2-1 MUX, and adders.
Inverter- a 4-bit word inverter is designed using buses as seen below.
   

   
I made sure to 'check & save' to verify it was labled correctly.

   
Symbol is then created

     
A simulation using this array is set as specified in the laboratory.
   

   
The simulation is analysed based on the three different capacitive loads (100f, 500f, and 1p) and no load, as follows
   

   
As seen in the plot, the capacitive loads affects the output rising and falling times. According to the relation, time_delay=0.7RC, the resitance is represented by the equivalent the resistnace in the inverter, and the capacitance by each load, so as the capacitance increases the time delay increases. That is what we see in the simulations; for the 1pF load in takes more time to charge the capacitance, so it increases the rising and falling time. Instead, for no load, it only depends on the Cox capacitance in the inverter.
   
NAND, NOR, AND, and OR gates
In this part, the schematic and simulation of 8 bit word gates is designed as follows
   

Gate	Schematic	8 bit schematic	Symbol
INV
NAND
NOR
AND
OR

Gate	Schematic	Simulation
Inv		Lab7_pictures/sim_8inv_sim.jpg
NAND
NOR
AND
OR

   
For simplicity, all the 8-bit input A and B for all gates were shorted, but they still output an 8-bit value.
It is seen from the above table that all the gates worked properly, and for each load in  each bit the delay is observed. The time delay increases as the load capacitance increases.
   
2-to-1 MUX (multiplexer)
Now, the operation of a MUX is analize from the following schematic.

   
The symbol is then created.

   
The 2-to-1 MUX is simulated.
        
   
A 2-to-1 multiplexer (MUX) is a selector that points which of the two inputs signals is output by a control signal. From the above schematic, if S=1 and Si=0, the output is the same as A, and if S=0 and Si=1, the output is the same as B, as shown in the above simulation.
From the plot, between 0 to 400ns, S=1 and Si=0, the output Z changes as A changes. From, 400ns to 800ns, the output Z behaves as B.
In a 1-to2 demmultiplexer (DEMUX), the input Z is output through either A or B depending of the selector. If S=1, output A is same as Z, and if S=0, output B is same as Z. To achieve this, from the MUX schematic, all we have to do is change inputs A and B as output, and output Z as input. The selectors remain the same. The corresponding simulation is shown below.
     

   

Next, an 8-bit word 2-to-1 MUX is designed. Since S and Si are complementary, an inverter is used to get one input selector.
   

   
The symbol of this schematic is instantiated in a simulation as follows.
   
 
 
For sake of simplicity,  both 8 bit inputs, A and B, are the same as shown in the above schematic. However, we expect that it generates 8 output signals which will be all the same as shown below.
   
 
   
As seen in the plot, when Selec is high, all 8 bit Z outputs (Z<0>, Z<1>, Z<2>, ....) are the same and equal to A, and when Selec is low, the outputs are the same as B.
   
Full Adder and 8-bit Full Adder
As specified in the laboratory requirements, the schematic of a full adder using 6u/0.6u NMOS and PMOS is designed. The inverter used before in this lab is instantiated as part of this schematic
   

 
The symbol is created from the above schematic.
         
   
Next, a 8-bit word adder is drafted using the above full-adder eigth times, such that the carry out of the first full adder goes to carry in of the next one. There is 1-bit input carry in. The ouput is an 8-bit S and 1-bit carry out (Cout).
   

   
The symbol is then created.
         
   
The opartion of this cell is now simulated.

     
Again, for sake of simplicity, both 8 bit inputs A and B are connected to the same voltage pulse source, respectively as shon above. However, we expect to see an 8-bit output S.
The following table shows the expected results for some input 8-bit words.

Simulation
     

   
It is observed that the above simulation follows the addition example from the table. From that table, carry out (cout) is 1, only Z<0> is zero, and the rest Z outputs bits are 1, as expected.
Next, the full adder cell is laid out.
   

     
DRC to verify no errors were found

   
Etracted view
     
LVSing the schematic vs the extracted view:
     
   
Now, the 8-bit word adder is laid out, as seen below, and its corresponding extracted view.
 

   
 
   
Zooming in the layout to show the connection between carry out of one adder to carry in of the next one.
 
   
LVS (layout vs shematic)
    
   
This ends Lab 7 about basis of ALUs
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 here.
As always, back up of this lab was saved on my portable USB, Google drive account, and in the CMOS account drive.
     

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