Lab 6 - ECE 421L 

Authored by Stephanie Silic

silics@unlv.nevada.edu

October 19th, 2015

Lab Description: This lab consits of creating the schematics and layouts of a 2-nput NAND gate, a2-input XOR gate, and a Full Adder using two three NAND gates and two XOR gates, and confirming the operation of these gates with simulations.

I will present this lab in 4 parts:

• Part 1 -- schematic and layout of the NAND gate
• Part 2 -- simulation of NAND and XOR gates
• Part 3 -- schematic and layout of the Full Adder
• Part 4 -- simulation of the Full Adder

Lab Report:

Part 1 -- schematics and layouts of the 2-input NAND gate and 2-input XOR gate

Drafting the schematic of a 2-input NAND gate, with transistors of minimum length and a width of 6um.

The symbol I will use from now on in circuits for the NAND gate:

Now, we open a new cell view and begin the layout of the NAND gate, keeping in mind that it should be in a cell frame that is tall, so that we can snap it together with our XOR gate to make the Full Adder:

Now for the XOR gate:

The XOR gate will consist of 6 PMOS transistors and 6 NMOS transistors; the schematic is as shown below, and the symbol:

Now, we must create a layout for the XOR gate. With 12 transistors and all those connections, it proves more of a challenge than the simple NAND gate. We must ensure that each connection seen in the circuit above is made using poly1, metal1, or metal2 wires in the layout. After every few connections, I would perform the DRC, and often came up with minor errors: things like the metal wires being too close. The final layout looks like this: 

The layout passes the DRC:

In this layout, I made sure A, B, and AxorB could be easily routed to the NAND gate necessary for the FullAdder design. I did not need to have A' and B' routed all the way, however.

Now, we are ready to perform the Layout versus Schematic (LVS) check. I had two errors in my layout at first; one PMOS transistor was not connected to VDD, and I had failed to connect the AxorB node from between each group of double PMOS and NMOS transistors.

But finally, the LVS was successful:

Part 2 -- Simulation of the NAND and XOR gates

To check the operation of our logic gates, we construct the following circuit:

We need to check that the gates follow the values given by this truth table:
  

The pulse source for input A is set with a period of 1us, while the source for B has a period of 500ns. This will give all four possibilities in the truth table. The simulation gives the values expected, as shown below:
 

 
Part 3 -- Schematic and Layout of the Full Adder:
 
Now, we need to put these logic gates together to form a Full Adder. The schematic looks like this:
 

 
And the symbol I will use in the simulation circuit looks like this:
 

 
The layout went smoothly, and passed LVS the first time I tried. My layout for the Full Adder looks like this:
 

 
The DRC and LVS results are shown below:
 

 

 
Part 4 -- Simulation of the Full Adder
 
Finally, we need to ensure that the Full Adder gives the values specified by this truth table:
 

To do this, we set up the following circuit:
 


 

The 3 inputs are set similarly, with cin having a period of 500ns, B a period of 1us, and A a period of 2us. We do a transient analysis for 2us, and the simulation results are as expected:
 


   

The simulation gives the results of the truth table. When done from the extracted view the results are the same, as they should be:
 

This completes Lab 6.
 
All work backed up in Google Drive and on my PC:
 
     
 

   

Return to EE421L Fall 2015 page

Return to my labs