Lab 7

Lab 7 - EE 421L

Authored by Shada Sharif,

sharifs@unlv.nevada.edu

2 November 2015

Pre-lab work:

Lab Description:

This lab will be about using buses and arrays in designing inverters, MUX/DEMUX, full adders, and other logic gates.

Lab Report should include:

Experiment #1

The first part of the lab was to do the prelab which is going through Tutorial 5 from the website. In the lab we stated by making a ring oscillator that consists of 31 inverters connected all in series.
We had set vdd as 5 V and the output of the last inverter was connected back to the input of the first inverter and that is how we got an oscillator.

We plotted the output of the oscillator after setting the initial conditions and the result is shown below

We then created the same schematic as seen above but using buses and arrays. As well as array of inverters layout using the idea of making one layout and then starting a new layout and instantiating the layout made first as many times as we need.
We LVS the extracted array of inverter's layout with the schematic of the inverter, and simulate the schematic as well as the extracted.
When doing simulation for the schematic we first made the symbol and used that for simulation.

The waveform on the left is the one from the schematic, the right one is from the extracted.

This is showing that the simulation was indeed from the extracted layout.
After finishing tutorial 5 now it is time to start the lab, we first start by exploring the bus wires and creating arrays.
Shown below is the schematic used to make an inverter, and we create a symbol for it.
The the inverter is the same as from previous labs, and now we want to make a 4 bit inverter so we instantiate the inverter 4 time as well as name the pins accordingly as an array from 0 to 3 <3:0>.

We then do the same exact thing but using a bus, and the naming of the wire, as well as the instance name is made as an array.
We create a symbol of the 4 bit inverter
We test the operation of the 4 bit inverter by connecting loads to three of the four pins while the input is a pulse. input is a pulse.

We see how the capacitive load affects the rise and fall time due to the delay created from the capacitor. The bigger the load the higher the delay, and this can be seen when comparing the 100 fF waveform output, which is a small load, compared to the 1 pF. With higher capacitive load the inverter cannot supply enough current to drive the load the output comes out like that with a delay, and not as clean as the input.

Experiment #2

In this experiment, we start to make 8 bit logic gates, the same process follows as in doing the inverter.
We first create the schematic and then create a symbol for the schematic. Using the symbol creates we connect bus wires, and rename the instance and wires as an array of 8 bits <7:0>.

We test the 8 bit gates again by placing a capacitor at the output of few pins, while the input is a pulse.
We see in the waveform output how the no load pin shows us the operation of each gate to inputs A and B, and as the load increases the delay at the output increases and the circuit cannot drive the bigger load anymore.

Experiment #3

We start by examining the MUX/DEMUX and how it operates.
The schematic of the MUX is seen below, and we create a symbol for the schematic.

A MUX is basically a selector, a 2-1 MUX have two inputs, a control signal, and an output. If the control signal is 0 the output is the same as input B, and if it is 1 then it is as input A. It is like a switch changing between two inputs depending on the control signal.
This operation can be seen in the above waveform, when input S is low the output Z is the same as input B, and when S is high, output Z is the same as input A.
To have the MUX act as a DE/MUX as well we would just change the the output of the MUX and the input of the DE-MUX and the inputs of the MUX as the outputs of the DE-MUX.
We notice that S and Si are the same as having an inverter between both inputs so we modified the schematic by adding the inverter used in the beginning of lab and made an new symbol for the schematic.

Now if we do the same schematic done above we would get the same exact waveform.

The following is the schematic for a DE-MUX as well as the waveform output to show its operation.
We see that the input signal is from Z, and the controlling factor here is S. When S is high the input Z outputs from A which output B is random, and when S is low Z outputs in B which A is random.

Now we make an 8 bit MUX/DEMUX, using the schematic that includes the inverter and creating symbol using bus wires and instance name as an array.
We use the symbol created and have different inputs at two pins from the 8 bit MUX. The output waveform is shown below and verifies that the MUX works properly.

Experiment #4

The last part of this lab is about making a full adder, we start by making the schematic of the full adder and creating a symbol for it. In the schematic we again used the inverter from exp. 1.

To test the operation of the full adder we use pulse inputs at inputs A,B,Cin and see how the outputs Sum, Carry-out are. From the waveform we see that the circuit is working properly, for example; when inputs are A=1,B=1,C=1 outputs are S=1,Cout=1.
We now start with the layout, we extract the layout when done, DRC to make sure no error exists, and LVS the schematic from above with the extracted layout.

Next step is to make an 8 bit adder schematic and layout, so we start with the schematic by using the symbol we made for the 1 bit adder and using bus wires and array instance name.
We create a symbol of the 8 bit FA schematic, and move on to the Layout.
The layout was done using the 1 bit layout done previously, we simply connected the Carry in to the Carryout of the Adders and renamed the pins of the 8 bit adder using < > so that they are in an array and match the schematic. We DRC, and LVS as always.

We see from the output waveform that the FA follows the truth table of a FA.
The second simulation shows when the input is a constant 1 so 1111-1111 and constant 0 so 0000-0000 and carry in becomes 1 after a set time we see that the output S is 1111-1111 and Cn_1 is 0 but when carry in is 1 now the output S is 0000-0000and Cn_1 is 1.

Backup of the Lab

Lab 7 zipfile