Lab 5 - EE 421L 

Authored by Shada Sharif,

sharifs@unlv.nevada.edu

5 October 2015

Pre-lab work:

• Back-up all of your work from the lab and the course.
• Go through Tutorial 3 seen here.

• This lab will be about the design, layout, and simulations of a CMOS inverter.

• Schematic of the CMOS inverter.
• Layout of the CMOS inverter.
• LVS match and DRC no errors of the layout.
• Spectre simulations of the inverter along with capacitive loads.
• UltraSim simulations of the inverter along with capacitive loads.

• The first experiment was about making the CMOS inverter using a 12u/0.6u PMOS and 6u/0.6u NMOS.
• The first thing we did was create the schematic for the inverter along with its symbol. Notice in the schematic for vdd a supply net and not an actual dc source. 

• After making the schematic we start with the layout of the CMOS, while checking that there is no errors with DRC along the way. 
• We made sure that all the pins are named the same in the layout to avoid mismatching errors.
• After that we extracted the layout and then LVS the extracted layout along with the schematic to check matching. 

• The second experiment was similar to the first one but this time we multiplied the width of the PMOS and NMOS by 4 as if we have 4 of the CMOS in parallel. 
• The schematic was done again, and then the symbol was created. 
• The layout was done as shown below and the extracted layout follows. 
• We DRC the layout and then LVS the extracted layout with the schematic to check for matching.

• Now that we have the layout, schematic matching we start with simulation. We will be conducting two types of simulations with spectre and UltraSim which can only be done in transient analysis.
• The simulation is done with different capacitive loads, and the schematic used is as shown below
• The schematic was done using the symbol made in experiment #1.
• The load is changed everytime accordingly for each waveform.

	Spectre	UltraSim
100 fF
1 pF
10 pF
100 pF

• We notice that the simulations with both spectre and UltraSim are similar, and UltraSim gives a more accurate waveform output. 

• The last experiment is repeating experiment #3 but with the CMOS inverter 2, which has the widths of both the NMOS and the PMOS multiplied by m=4. 
• The schematic used this time is using the symbol created in experiment #2, and then capacitive load was added everytime accordingly.

	Spectre	UltraSim
100 fF
1 pF
10 pF
100 pF

• We see in the calculations below that the CMOS inverter has an output resistance and when a load added, a capacitive load, we get and RC delay for the output.   

• We first notice that the output is inverted since this is an inverter, and as the capacitive load increases the bigger the RC delay this means it takes longer for the capacitor to charge. Thus we see how output as the capacitor value increase take longer to reach from 5V to 0V since the time it take the capacitor to charge and discharge is RC. 
• So in the first inverter we see limitations in the value of the capacitance the circuit can drive since it takes longer time for the output to change.
• In the second inverter we see that since the mosfet is 4 times the width as if they are placed in parallel that means they have bigger current, which can be seen in the formula above, and lower output resistance so it can drive bigger loads better than the first inverter since it can supply more current. 
• We can see the limitations in the second inverter starts to appear when the load is 100 pF as in the first inverter the limitations started from 10 pF

•  The lab backup was saved to GoogleDrive, and the zipfile is attached below for all the schematics, layouts, and simulations.  

Return to EE 421L Labs