Lab 4 - EE 421L 

Authored by Shada Sharif,

sharifs@unlv.nevada.edu

28 September 2015

Pre-lab work:

• Back-up all of your work from the lab and the course.  
• Read through this lab before starting it.
  
• Go through Tutorial 2 seen here. 
• In the simulations in this lab the body of all NMOS devices (the substrate) should be at ground (gnd!) and the body of all PMOS devices (the n-well) should be at a vdd! of 5V.  

• This lab will include IV characteristics and layout of NMOS and PMOS devices in ON's C5 process.

• IV curves of the NMOS and the PMOS.
• The layout of the NMOS and the PMOS. 
• Layout of the NMOS and PMOS attached to 4 probe pads.

• The first things we did in this lab was to copy the files done in Tutorial 2 to a new folder to use in this lab.
• We first start with making the NMOS schematic and then generating a symbol for it so that we can use it in the IV curves.
• We make sure that the body is connected to gnd! (universal ground).

• The first part of this lab was about making NMOS schematics and then varying the voltages VGS or VDS or both at the same time. 
• The first IV curve was ID vs. VDS where VGS varies from 0 to 5V in 1V increments, and VDS varies from 0 to 5V in 1mV increments.
• The NMOS had a length of 600 nm and a width of 6 um.

 

• To generate this waveform we plotted the current at the drain vs the voltage of the drain-source, while varying the gate-source voltage. 
• We notice that there is 5 traces in the waveform above, each waveform represents a different VGS voltage starting from the bottom of 0V VGS to the top of 5V VGS.
• The second IV curve was ID vs VGS where VDS was fixed at 100 mV and VGS varies from 0 to 2V in 1mV increments.

 

• This is again a waveform generated by plotting the drain current vs the gate-source voltage. 
• In this waveform we see that the mosfet starts to conduct current after a certain voltage and this is called the threshold voltage so when VGS>Vth thats when the curve starts increasing.

• We do the same thing we did for the NMOS again for the PMOS by starting with the schematic and the symbol.
• We have the body this time connected to vdd!.

•  The first PMOS IV curve was ID vs. VSD where VSG varies from 0 to 5V in 1V increments, and VSD varies from 0 to 5V in 1mV increments.
• The PMOS had a length of 600 nm and a width of 12 um.
• Notice how the body pin name was changed below to B instead of vdd! due to the problem of not generating a vdd! pin when the symbol was created from the schematic, thus the pin was just connected to vdd when the IV plot was made.

 

•  Notice how the source here is not connected to ground, and this has to do with the PMOS structure where we need to connected the source to vdd in order to create enough potential for the mosfet to conduct. We notice a very similar waveform output with the same idea that each plot represents a certain VSG value. 
• The second PMOS IV curve was ID vs VSG where VSD was fixed at 100 mV and VSG varies from 0 to 2V in 1mV increments.

 

• Now we start with layouts, the first layout we do is a NMOS layout of 6u/0.6u connected to 4 probe pads,
• We start with copying the probe pads from HMWK5 where we did Tutorial 6.
• We have the pad layout, the pad schematic, and the pad symbol.

• Now we layout the NMOS 
• We have below the NMOS layout as well as the extracted layout showing all the pin connections.

 

• We DRC the layout without any errors and then we LVS with the NMOS schematic used in the NMOS IV curves in experiment #1.

• Now we start by connecting the NMOS with 4 probe pads, and we do that by first extending metal 1 from the pins of the NMOS, then use via to connect metal 2, then via 2 to connect to metal 3, and lastly metal3 to connect to the probe pads. 

 

• Above is the layout of the NMOS and the 4 pads as well as the extracted layout below.
• We DRC without any errors, and then to LVS we create a new schematic using the symbols created for the pad and NMOS and replicate the same node names and layout.

 

• We use the same pads shown in experiment #3, and layout a PMOS 12u/0.6u that will be connected to 4 probe pads.
• We then DRC without any errors and LVS the layout with the schematic done in experiment #2.

• We do the same thing again from the NMOS layout for connecting PMOS to the pads.
• Then we DRC and make sure there is no errors and LVS with the schematic shown below.

• All the work was backed up to Google Drive    

 

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