Lab 3 - EE 421L 

Authored by Shada Sharif,

sharifs@unlv.nevada.edu

21 September 2015

Pre-lab work:

• Back-up all of your previous work from the lab and the course.
• Finish Tutorial 1 seen here. 

• This lab will focus on the layout of the 10-bit DAC we designed and simulated in Lab 2.

• The layout of the n-well resistors, the resistor divider, and the DAC. 
• DRC of each of the previously mentioned, and LVS with the schematic from Lab 2.
• Simulations from the extracted layout and compared to the schematic simulations.

• The first thing we did in this lab was to copy all the files from Lab 2 to Lab 3 library in Cadence. We then used the n-well to layout a 10k resistor as discussed in Tutorial 1. 
• For selecting the length and width we used the equation for finding the resistance, in order to do so we first found the sheet resistance for MOSIS process which is 800 ohms/square. 
• After knowing the length and width values we now are ready to draw the n-well resistor, we use the n-well layer, draw a rectangle, and then we edit the properties as shown below.  

       

• We see here in the extracted layout the value of the resistor turned out to be r=10.21k ohms which is pretty close to 10k ohms.
• We could measure the resistor length and width from the layout by using the ruler which is binkey k as shown below, we measured the length to be 56u and the width 4.5.u as calculated earlier and we also measured the resistor while includes the ntap as shown in the next picture. To remove/clear all the rulers we just used bindkey K.

• Now after having the resistor we are ready to start laying out the DAC. We first do the resistor divider as shown below, and connect the resistors using metal1 as well as labeling pins using metal1. The pins labeled were the same name as in the schematic for the LVS to match later.
• We DRC along the way to check the spacing is right and after we are done we extract the layout and LVS with the schematic from Lab 2.

•   After saving the resistor divider, we open a new layout and start stacking the DAC as shown below. Each resistor in the DAC is laid out in parallel having the same x-position but varying y-positions. 
• The left picture is the layout and the right picture is the extracted layout.
• We notice there is 10 resistor dividers where each one represents 1 bit so for a 10-bit DAC we used 10.
  

     

• Zoomed in pictures are shown below to show the labeling of the pins, we have all the bits/inputs of the left, an output, and a ground pin.
• All input and output Pins are metal1.

 

• Notice in the picture (the red arrow) above an extra 10k n-well resistor was added so the the bottom total resistance is 20k ohms.
• As always we DRC with no errors and we then LVS the extracted DAC with the DAC schematic from Lab 2.

__________________________________________________________________________________________________________________________________________
       
Experiment #3

• We lastly produce the same simulations we did in Lab 2 for the schematic again for the extracted layouts.
• In order to do so, we first use the simulations that were copied from Lab 2 over to Lab 3 library as shown below, and we launch the ADE L as normal. For the ADE L to simulate the extracted layout we go to Setup -> Environment and we add the word extracted before schematic in the first line as shown below.
• When we run the ADE we get the same simulations, and to make sure that the simulations are from the extracted layout we could check from ADE. We go to Simulation -> Netlist -> Display and in the window that pops-up we see next to View name:extracted, which means this is the simulation for the extracted layout.
• This step was done for all the simulations to check that the extracted layout was simulated, but it is only shown here once.

   
   
       

• The simulations are numbered below:
• Simulation 1 is for the DAC when it is replaced with the ideal DAC in the circuit along with the ADC. We see it is not different than the schematic simulation.
• Simulation 2 is when the DAC had a pulse input from pin 9 and all the other pins were grounded, the output had a 10pF load and we got an RC delay for the circuit(Notice in extracted simulation voltage measured was 1.26V not 1.25V thats why delay number is a bit more).
• Simulation 3 is when the DAC and ADC were connected and we had a 10k ohms resistor load at the output.
• Simulation 4 is when the load was changed to a 10pF load.
• Simulation 5 is when the load was an RC of 10k ohms and 10pF.
• We notice that the simulations are pretty much the same in both schematic and extracted layout, which is expected.

	Simulations from the schematic	Simulations from the extracted layout
1
2
3
4
5

Return to EE 421L Labs