Lab 7 - Emmanuel Sanchez

Lab 7 - EE 421L

Authored by Emmanuel Sanchez,

Email: sanch512@unlv.nevada.edu

10/18/2015

Lab description:

Using buses and arrays in the design of word inverters, muxes, and high-speed adders.

Pre-lab work

31-stage ring oscillator

Schematic

Layout

Simulation

Lab Report:

Inverter schematic & symbol:

Testing the inverters with different capacitive loads:

We can see that increasing the capacitance at the load, increases the time delay across the inverter.

Schematics and symbols of 8-bit gates:

Schematic for 1-bit NOT
Schematic for 8-bit NOT	Symbol for 8-bit NOT

Schematic for 1-bit NAND
Schematic for 8-bit NAND	Symbol for 8-bit NAND

Schematic for 1-bit AND
Schematic for 8-bit AND	Symbol for 8-bit AND

Schematic for 1-bit NOR
Schematic for 8-bit NOR	Symbol for 8-bit NOR

Schematic for 1-bit OR
Schematic for 8-bit OR	Symbol for 8-bit OR

Testing the gates!

Testing the 1-bit gates for all possible combinations of A and B (00, 01, 10, 11):

We can see the outputs of the gates are correct when compared to the following truth tables:

AND

NAND

NOR

MUX/DEMUX Exercise:

MUX/DEMUX Schematic

Schematic of 1-bit 2-1 MUX	MUX Symbol
Schematic for MUX Simulation	Schematic for DEMUX Simulation
MUX Simulation In the MUX simulation we see that: When the selector line S is equal to 1, the signal at Z goes to A. When the selector line S is equal to 0, the signal at Z goes to B.	DEMUX Simulation In the DEMUX simulation we see that: When the selector line S is equal to 1, the signal at Z goes to A. When the selector line S is equal to 0, the signal at Z goes to B.

Creating and testing 8-bit 2-1 MUX

Schematic of 8-bit MUX	8-bit MUX symbol and schematic used for simulation
8-bit inputs for MUX simulation --> A<7:0> = 10010001 --> B<7:0> = 11011011	8-bit output from MUX simulation --> Z<7:0> = 10010001 when S = 1 --> Z<7:0> = 11011011 when S = 0