Lab 3 - EE 421L 

Authored by Russ Prado,

prador@unlv.nevade.edu

9/14/2015

Complete Tutorial 1

20k n-well:

Post-Lab:

In this lab, we recreated the 10-Bit DAC with the layout techniques learned from Cadence Tutorial 1. We used the 10k n-well to recreate the DAC:

Don't forget to DRC the schematic to layout to make sure there are no errors.

If there are no errors, extract the layout. Now, we have to LVS the layout so that we can compare the layout with the original schematic of the layout to make sure we had no errors in creating the layout.

If the LVS runs successfully, this mean that the layout we created is identical to 10-Bit DAC from Lab 2.

Don't forget to back-up your Lab3 files

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