Lab 7 - ECE 421L

Co Nguyen

10/16/2015

Lab description:

Using buses and arrays in the design of word inverters, muxes, and high-speed adders.

Pre-lab:

Review tutorial 5 can be found here. Seen belwo are some images from the complentention of Tutorial 5.

Schematic of ring _osc:

Sim of ring_osc:

click on image

Layout of ring_osc (DRC no error):

click on image

Extracted the layout of ring_osc:

click on image

LVS and Output of ring_osc:

click on image

Post-lab:

Design and Simulation of a 4-bit Inverter

1-bit Inverter:

Schematic	Symbol

4-bit Inverter:

Schematic	Symbol

4-bit Inverter simulation:

Schematic	Simulation

The increase of signal delay from out<0> to out<3> which is due to increasing the output capacitance. The capacictance as a bucket charges water, the bigger bucket needs to take long time to fill with water. So, the bigger capacitance has the greater delay.

Design and Simulation of an 8-bit NAND Gate

1-bit of NAND Gate:

Schematic	Symbol

8-bit of NAND Gate:

Schematic	Symbol

8-bit of NAND Gate simulation:

Schematic	Simulation

The increase of signal delay from out<0> to out<7> which is due to increasing the output capacitance. The capacictance as a bucket charges water, the bigger bucket needs to take long time to fill with water. So, the bigger capacitance has the greater delay.

Design and Simulation of an 8-bit NOR Gate

1-bit of NOR Gate:

Schematic	Symbol

8-bit of NOR Gate:

Schematic	Symbol

8-bit of NOR Gate simulation:

Schematic	Simulation

Design and Simulation of an 8-bit AND Gate

1-bit of AND Gate:

Schematic	Symbol

8-bit of AND Gate:

Schematic	Symbol

8-bit of AND Gate simulation:

Schematic	Symbol

Design and Simulation of an 8-bit Inverter

1-bit of Inverter:

Schematic	Symbol

8-bit of Inverter:

Schematic	Symbol

8-bit of Inverter simulation:

Schematic	Simulation

Design and Simulation of an 8-bit OR Gate

1-bit of OR Gate:

Schematic	Symbol

8-bit of OR Gate:

Schematic	Symbol

8-bit of OR Gate simulation:

Schematic	Simulation

2-to-1 DEMUX/MUX

MUX Operation and simulation:

Schematic	Simulation

Signal A= 5V and B=0V

When S=1 then Z = 5V

S=0 then Z = 0v

The purpose of a MUX is ouput one signal from multiple input signals

DEMUX Operation and simulation:

Schematic	Simulation

When S (select) =1 that A(Output)= Z(Input)

S(select) = 0 that B(Output)=Z(Input)

The purpose of a DEMUX is to choose an output path based on multiple outputs given one incoming signal.

Design and Simulation of an 8-Bit MUX/DEMUX

1-Bit MUX/DEMUX

Schematic	Symbol

8-Bit MUX/DEMUX

Schematic	Symbol

8-Bit MUX & Simulation:

Schematic	Simulation

The increase of signal delay from out<0> to out<3> this is due to increasing output capacitance. The capacictance as a bucket charges water, the bigger bucket needs to take long time to fill with water. So, the bigger capacitance has the greater delay.

8-Bit DEMUX & Simulation:

Schematic	Simulation

The increase of signal delay from A<2> from B<0> to B<3> this is due to increasing output capacitance. The capacictance as a bucket charges water, the bigger bucket needs to take long time to fill with water. So, the bigger capacitance has the greater delay.

Design and Simulation of an 8-Bit Full Adder

1-Bit Full Adder:

Schematic	Symbol

8-Bit Full Adder:

Schematic	Symbol

8-Bit Full Adder & Simulation:

Schematic	Simulation

As we can see, when A = 11111111 and B = 11111111, with a C in = 0 and Cout = 1. We have result Output = 11111110 as expect 8-bit Full Adder is working correctly.

Layout and extracted of an 8-Bit Full Adder

Layout of 8-Bit Full Adder:

Left view of 8-Bit Full Adder:

Right view of 8-Bit Full Adder:

Extracted:

Full Cell	Inside 1 cell

DRC and LVS (no error):

DRC (no error)	LVS (no error)

Saving my work:

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