Lab 6 - ECE 421L
Co Nguyen,
10/16/2015
Lab
description:
Design, layout, and simulation of a CMOS NAND gate, XOR gate, and Full-Adder.
Prelab:
The lab begins with completing Tutorial 4 seen here. Seen below are the images from the completion of Tutorial 4.
This is a schematic of NAND gate by connecting 2 of PMOS (6u/600n) and 2 of NMOS(6u/600n).
Following is the NAND gate symbol:
Connecting NAND gate to Vpulse and tied Output to 100f of capacitance:
Simulation the NAND gate following:
Layout the NAND gate:
Extract the layout:
LVS and Output layout:
Postlab:
This is the schematic and symbol of NAND, XOR, and Full_Adder
| Gate | Schematic | Symbol |
| NAND |  |  |
| XOR |  |  |
| Full-Adder |  |  |
| Gates | Layout and DRC without error | LVS and Output without error |
| NAND |  |   |
| XOR |  |   |
| Full-Adder |  |   |
NAND gate truth table
XOR gate truth table
Full_Adder truth table
| A | B | Cin | S | Cout |
| 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 1 | 0 |
| 0 | 1 | 0 | 1 | 0 |
| 0 | 1 | 1 | 0 | 1 |
| 1 | 0 | 0 | 1 | 0 |
| 1 | 0 | 1 | 0 | 1 |
| 1 | 1 | 0 | 0 | 1 |
| 1 | 1 | 1 | 1 | 1 |
| Gates | Schematic | Simulation |
| NAND |  |  |
| XOR |  |  |
| NAND and XOR |  |  |
| Full-Adder |  |  |
Back up my work
Return EE 421L Labs