Lab X - ECE 421L 

Mari Gilligan                                                                                                                                  Email:mgill19@unlv.nevada.edu

10-17-2015

  We will go through the Tutorial 4 for our prelab :

Back up your Ducumnets as usual:

in order to creat the bakup,go to Moba-x term and log in to Csimcluster.ee.unlv.edu, when you sign in type  this sentence (tar-cvf backupdate.tar CMOsedu/).

using this commend will creat the tar file with all projects saved.after you creat the tar file type this commond ( gzip backupdate.tar).this command helps us to have the back up dpcuments in smaller size file.

http://cmosedu.com/jbaker/courses/ee421L/f15/students/mgill19/Lab6/Lab6/cad39.JPG

Luanch virtuoso;copy Lab5 to Lab6 in the Library manager,and click on the update instatnces when you are copying .

we are going to have a Nand gate ,so will start by using the inverter from lab 5,change the Pmos to 6.0u/6.0u and do the same for Nmos as well.wire things up and you should have this schematic :

http://cmosedu.com/jbaker/courses/ee421L/f15/students/mgill19/Lab6/Lab6/cad1Lab6.JPG

create the symbol view from your schematic and delete everything in it ,Like this:

http://cmosedu.com/jbaker/courses/ee421L/f15/students/mgill19/Lab6/Lab6/cad2.JPG

simulation of the gate operation ,make a schematic view of a cell called sim_nand 2 and draft the following :

http://cmosedu.com/jbaker/courses/ee421L/f15/students/mgill19/Lab6/Lab6/cad3__.JPG

setting the source and the analysis as follows:
Note:  If you are using Golobal stimuli ,you cany have  a DC source as well
http://cmosedu.com/jbaker/courses/ee421L/f15/students/mgill19/Lab6/Lab6/cad4.JPGhttp://cmosedu.com/jbaker/courses/ee421L/f15/students/mgill19/Lab6/Lab6/cad5.JPG
http://cmosedu.com/jbaker/courses/ee421L/f15/students/mgill19/Lab6/Lab6/cad3.JPG

ADL->Model libraries->for setup Models.
After setting ,check and save and run the simulation and you should get this:

http://cmosedu.com/jbaker/courses/ee421L/f15/students/mgill19/Lab6/Lab6/cad6.JPG

Next close nad save all the open cells ,Use Library manager to open the Nand layout cell view ,which shows the invereter ,since we copied it at the beginign

http://cmosedu.com/jbaker/courses/ee421L/f15/students/mgill19/Lab6/Lab7/cad3.JPG


Get ride of the metal1 fron the Ntap to the source of the pmos and delete the vdd! pin.
copy the Pmos cell as seen below.
http://cmosedu.com/jbaker/courses/ee421L/f15/students/mgill19/Lab6/Lab6/cad8.JPG    
we need to copy the Pmos in such a way that would overlap the left pmos and then chnage the ntap cell,so that has 5 columns of contacts ,DRC the layout.

http://cmosedu.com/jbaker/courses/ee421L/f15/students/mgill19/Lab6/Lab6/cad9.JPG


Next move the ptap cell so its under the nmos cell,and then go ahead and copy the nmos and overlap it with the first like we did for the nmos .make sure the pin names are showing,.BPin is (input),and Vdd! and gnd! are  (inputoutput) .
http://cmosedu.com/jbaker/courses/ee421L/f15/students/mgill19/Lab6/Lab6/cad10.JPG
Since we notice we have the metal between the Mosfets that we dont need. it,select both mosfets then flatten then (this will make the nmos cell to be no longer cells but rather rectangles in the layout).
Deselect thet prevouse pins Geometrics.This will ensure that the goemetric information of flattend pins is not preserved.
we dont want pins or the  pin information in our layout .

http://cmosedu.com/jbaker/courses/ee421L/f15/students/mgill19/Lab6/Lab6/cad11.JPG

now delete the metal1 and contacts between the two nmos.add the metal1 to gnd! aand vdd! (two places) and conncet the drains of the two pmos to the drain of the nmos.DrC your layout.
http://cmosedu.com/jbaker/courses/ee421L/f15/students/mgill19/Lab6/Lab6/cad12.JPG
extract the layout and Lvs your layout:


http://cmosedu.com/jbaker/courses/ee421L/f15/students/mgill19/Lab6/Lab6/cad14.JPG

save and close everything.this concludes Tutorial4.

End of Prellab4


stimulation of 2_Nand Gate ,by creating the new schematic view for the simulation ,we will be using two pulse inputs ,set your nmos and pmos to be 6.0u/6.0u for both .
im using the 2_pulse to be mu inputs :

Launch the ADE_L and perform transiant analysis:
we need to reapeat above instructure for our XOR gate as well:
so start with creting your schematic first ,this process is a little complicated so make sure that pay close attention:

http://cmosedu.com/jbaker/courses/ee421L/f15/students/mgill19/Lab6/Lab6/cad15.JPG
next step is to create the symbol:


http://cmosedu.com/jbaker/courses/ee421L/f15/students/mgill19/Lab6/Lab6/cad16.JPG

the most important part to creat the layout :

http://cmosedu.com/jbaker/courses/ee421L/f15/students/mgill19/Lab6/Lab6/cad19.JPG

check and save and run the DRC on your layout:

http://cmosedu.com/jbaker/courses/ee421L/f15/students/mgill19/Lab6/Lab6/cad20.JPG

now we get the extracted from the layout by go to ->verify->extract:
then open the extracted view and run the LVS :

http://cmosedu.com/jbaker/courses/ee421L/f15/students/mgill19/Lab6/Lab6/cad21.JPG
Next test the XOR gate like this by sing the Nand gate and run the transient Analysis:


http://cmosedu.com/jbaker/courses/ee421L/f15/students/mgill19/Lab6/Lab6/cad31.JPG

http://cmosedu.com/jbaker/courses/ee421L/f15/students/mgill19/Lab6/Lab6/cad27.JPG

now that we are familier with the process and Nand and XOR,we are going to build the full adder,and should be similar to what i have here:

http://cmosedu.com/jbaker/courses/ee421L/f15/students/mgill19/Lab6/Lab6/cad28.JPG
after we get the schematic we need to get the symol view as we alwyas do :
http://cmosedu.com/jbaker/courses/ee421L/f15/students/mgill19/Lab6/Lab6/cad24.JPG


Layout of our Full adder:
ill be using the metal2 for my conncetions and couple of pins,when you do your layout you might have extra vdd nd Gnd on the top of each other,so go ahed and delete the extra ones,.make sure your connction are correct other wise you will get an error and since its a complicated process ,it might not be easy to see your maistkes,.
your layout should be like this:
check and save and run the DRC:
http://cmosedu.com/jbaker/courses/ee421L/f15/students/mgill19/Lab6/Lab6/cad25.JPG




Run the LVS:
http://cmosedu.com/jbaker/courses/ee421L/f15/students/mgill19/Lab6/Lab6/cad36.JPG

now your full adder need to simulate with 3input pulse sources:

http://cmosedu.com/jbaker/courses/ee421L/f15/students/mgill19/Lab6/Lab6/cad38.JPG
I try my Analysis for 100ns,And thats my simulation results.

http://cmosedu.com/jbaker/courses/ee421L/f15/students/mgill19/Lab6/Lab6/cad37.JPG



now we need to simulate this schemtic:


http://cmosedu.com/jbaker/courses/ee421L/f15/students/mgill19/Lab6/Lab6/cad32.JPG
http://cmosedu.com/jbaker/courses/ee421L/f15/students/mgill19/Lab6/Lab6/cad33.JPG



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