Project - ECE 421L
First, I like to set up a little grab-bag schematic to have anything needed handy (instead of instantiating everything).
Make the transmission gate schematic as follows. This will be used in
the D-Flip Flop/T-Flip Flop schematics (Also, the VDD pin will connect
for higher level instantiations).
Create a symbol for the transmission gate like the following.
Let us create the resistors and symbols for both the 10k and 25k ohm resistors like the following:
Run
a little sweep on the resistors to make sure the current is correct. We
can simply step the voltage up in a DC sim. For the 10k we have (5/10k =
500uA):
Another sim for the 25k resistor:
The voltage divider is as follows:
The sim should complete reflecting accurate voltage division.
We can make the schematic from the voltage divider as follows. Note the symbols for the 10k and 25k resistors were drawn out in their respective cell views.
Let's also set up our gates (copied from the previous lab) with a common VDD pin for linking together:
We now make our NMOS schematic:
Run a parametric analysis:
Our sweep should look like this (We've seen this on enough quizzes):
Set up our pmos sim schematic as follows.
Sweep VSG for the pmos:
Now,
let's set up the ring oscillator (Notice there is a vdd pin present. I
did this to connect all lower level circuits to a common, non-global
VDD. I wasn't sure if it work initially, but in the end, the counter
sims and everything else worked as expected - just make sure to connect
everything to vdd at ALL levels.):
Create a symbol for the ring oscillator.
We run a transient on it to make sure it is working correctly.
Next, we make the schematic for the D-Flip Flop like the following.
Note, this one contains the clear function which is invoked by the NAND
gates instead of inverters.
Now we can create the symbol for the DFF (with 'clear') like below.
At this point, it is a good idea to set up a simulation schematic to make sure the DFF works as expected.
I set these values to send a pulse to the D input
I set the clock signal as follows
Run the simulation like the following. For the clock, the
width was 20n, and the period was 50n, the D was those values doubled,
and the clear was double the values of D.
I set the Clear to last twice as long as the D input, so a
comparison can be made between when it is active and when it is
inactive.
As per the truth table of the DFF with the Clear, the waveform follows this pattern
Now that the D flip flop works, I chose to convert it to a T-Flip Flop, to make the counter design more intuitive.
There are some minor adjustments made to the DFF to make the TFF (Note-
this is an old screenshot before adding the vdd pin, for illustration
purposes)
Now we make the TFF symbol
At this point we can make the simulation schematic for the TFF using
voltage periods set as before. I just ignored the floating pin warnings.
This is for a quick sim only.
Since clear was confirmed to be working, I set it to 5V. When T is low, Q
is 0, Qnot is 1. When T is high, on the rising edge of the clock Q and Q
not toggle (complementary).
Following the waveforms, the T flip flop works similarly to the D flip flop, with some noticeable differences.
The truth table for the T Flip Flop is as follows
Now we can make the counter. The first stage of the counter looks as follows.
The next repeating stages up until the last bit looks as follows. Since these repeat, they can be turned into a symbol.
I just called this symbol the Counter Primative.
The entire counter schematic looks like the following. NOTE the bus on
top is for each Q out. We ignore the Qnot, so I placed a noconn to
minimize Cadence nag-screens.
Of course, since it is one of those nasty non-sim schematics, it is good to turn it into a nice little box.
I set up the sim schematic like the following.
It is important to get the timing right for the pulses. For instance,
setting the clock for 2n, then the up/down for 8X as long with 16X
period, and clear for 16X, and 32X the period provides all of
the waveforms necessary to make sure it is working as expected.
If you like taking the 'scenic route', by all means use spectre and
enjoy a relaxing wait while running the sim. For me, Ultrasim got the
sim completed relatively quickly.
Our final waveform should look like this:
LAYOUTS:
Now we begin out layouts. Below is the layout for the D flip flop with clear and DRC it.
Make sure the LVS matches the original schematic for the D Flip Flop
The following is the layout of the NMOS with a multiplier of 8
Now we run the LVS.
Here is the layout for the NMOS with a multiplier of 10.
Make sure the LVS is successful.
Now for the Big NMOS with a multiplier of 64, the layout is as follows.
We run the LVS and make sure it is successful.
Now we lay out the PMOS with a multiplier of 8 and DRC it.
Run the LVS and make sure everything is copasetic
Let us now create the layout for the PMOS with a multiplier of 10.
LVS the PMOS with the schematic.
Now we lay out the big huge 64 multiplier PMOS and DRC it.
Run the LVS on it and make sure it matches up as expected.
Next, we lay out the ring oscillator with buffer as follows (and DRC it):
From here, run the LVS and make sure it is okay:
Now we set up the environment for simulating the extracted view:
The waveform is as follows:
Make sure we actually simulated the extracted view:
Let us lay out the TFF as follows. I did this vertically to minimize space.
Make sure we have the LVS success we are looking for.
Building off the TFF layout, we design the layout for the counter primitave as follows.
Make sure the counter primitave is LVS'ing the way it should be.
Lets make sure a few of the other gates are working correctly. DRC the layout for the inverter.
Successful LVS is a good LVS.
One of the other new layouts I did for this particular project was for the trans gate. Let us DRC and LVS this one as well.
As we hoped for-LVS Success.
Now an exciting layout for the voltage divider:
The LVS results are successful.
At long last, we lay out the counter. If all of the sub-layouts are nice
and compact, the final result can be pieced together nicely as well.
It is a good day when it LVS's the way we want.
Make sure it works as expected by sim'ing the extracted view.
The waveforms are as expected when running the extracted counter.
Make sure the netlist reflects the extracted view to verify we actually
sim'ed the extracted view and not the schematic and then let our work be
forever immortalized in a fabricated chip from MOSIS.
The zip folder for this portion of the lab is HERE
Backing up:
As for every lab, all work is backed up using my Dropbox account:
