Lab 7 - ECE 421L 

Authored by Jimmy Manone,

10/17/15

Prelab:

Following Tutorial 5 we first we make the schematic for the ring oscillator as follows



In the ADE L settings we set it up for 200ns transient



Set up the Convergence aids from this menu



The initial conditions as such should be set up as follows



Set up stimuli as follows



Our trace will appear as follows



Now we make the layout as follows



LVS this layout against the schematic



Next we delete VDD from the schematic and create a symbol for the ring oscillator as follows



Create schematic for the simulation as follows



Run the sim with the same settings as before and we should get the same result



Run it with extracted before schematic in environment settings and the display should be the same

Just to verify that we used the extracted view and not the schematic, check the netlist in ADE

Lab Report:

Create a schematic using the inverter, and set the instantiations to 4 along with in and out pins named accordingly




Create the symbol




Create the simulation schematic with the instantiation of the 4 bit inverter labelling the wires as seen below




We can create the AND gate by using the NAND gate and inverting the inputs as follows




Set up the simulation for the AND gate with this circuit




The simulation of the AND gate should appear as follows




The results match up with the truth table




Make sure you have a 6u by 600n PMOS in your arsenal for instantiation in the bigger layouts. These may need tweaking later.




Make the schematic for the NOR gate




Create a symbol for the NOR gate




Create a schematic to sim the NOR gate




The NOR waveforms will follow the NOR gate truth table




Create the schematic for the OR gate. Tip - just add an inverter to the NOR gate




Create the symbol for it




Create the sim schematic in order to simulate the new symbol




The simulation is correct as per the OR gate truth table




Now we want to array these gates. Starting with the inverter, we make the 8 bit version




Create a symbol for it.




Now we do the same thing for the AND gate. Here is the schematic.




Make a symbol for it




The schematic for the 8 bit NAND




Create the symbol




Schematic for the NOR




NOR symbol




the OR schematic




The OR gate symbol is as follows




Create the schematic that can be reused to simulate the various 8 bit gates.




We can simulate the AND gate and get results as follows




For a simpler simulation we can choose one bit of each to make sure the gate is functioning properly




Using a single bit of each array, we can determine that the gate does indeed work as expected. We can also try other bits in this fashion.





Using our schematic, we can now try the OR gate to make sure it is OR'ing the way it should.





The OR gate waveforms match up accordingly





Set up the NOR circuit for simulation





The NOR waveforms also match up, as they are complimentary to the OR waveforms





Now we can expand it a bit, so I will try bits 3, 4, 5 of each input and output to see if out NOR results are correct.





The simulation result for multiple bits reflects the correct result





Now we have done some sims on our gates to make sure they were working properly, it is time to build the MUX





The MUX works as follows





The MUX symbol is as follows





Now we do the DEMUX circuit





The typical DEMUX symbol is as such





Make the test circuit for the mux





Run the sim, and it should reflect the proper inputs and outputs for the MUX





Now create the 8 bit MUX using the inverter to eliminate the si pin





Create the symbol for the 8 bit MUX





We can set multiple voltages to cycle through the bit sequence for each input to make life a bit easier





The sim schematic for the 8 bit MUX is as follows





The simulation for the 8 bit MUX can be seen in the following diagram





Create the schematic for the full adder as per Fig 12.20 of the text





Make the symbol





Set up the schematic to sim our brand new full adder.





Our full adder simulation is good





Now we take a minute or two to re-layout this schematic and make sure it DRCs





Now we extract the layout and verify it LVSs against the schematic correctly





Now we try the extracted in the sim





Our transient analysis comes out the same, so we are good with the extracted sim





Make sure that the netlist reflects the extracted view





Now we will make the 8-bit version of the schematic with the pins set according to how the ring oscillator is set up in tutorial 5





Create the symbol for the 8 bit full adder





Out 8 bit Full Adder sim comes out as follows





And our schematic for the sim is as follows. Note - make the connections follow something like this, otherwise the Cin and Cout will not display





Now we lay out our 8 bit Full Adder like the following.





Make sure it DRCs properly





Make sure it LVSs against the original 8 bit schematic.





From here we will now simulate the extracted view to make sure it does what it is supposed to do.





And it does work in a lovely fashion.





To make sure we used extracted, check the netlist in the ADE Simulation menu

The backup is HERE

Backing up:

As for every lab, all work is backed up using my Dropbox account: