Now, let us edit the schematic so it appears as the following.
Lab 6 - ECE 421L
Prelab:
Following Tutorial 4, We will copy the inverter to a new cell nand2
Now, let us edit the schematic so it appears as the following.
Now, create the symbol for the NAND gate by deleting all but the pins and drawing the shape like the following
Next, set up and design the simulation schematic for transient analysis as sim_nand2_tran
Next we go to the ADE L and make sure to include the model libraries as follows
Set up stimuli in setup in the ADE L as follows
Set up the simulation settings as follows
Now we run the simulation, and the waveform reflects the output of the NAND gate.
Now we lay out the PMOS and NMOS as follows. Note, The metal layer could
not be deleted as per the instruction, though it DRCd properly.
The extracted view
After some unsuccessful LVS runs and trying to delete the middle layer
in the NMOS I used a workaround and changed all to n-active.
Lab Report:
Create the schematic for the xor gate as follows
Create the symbol for the xor gate
Create a schematic with pins for gnd and vdd for LVS
I created my layout as shown below.
Notice that some creative routing is necessary in order to make sure that each connection is routed properly.
More of this type of routing
It did not pass LVS - so there was a lot of tracing of routes. After some hours I figured out it was the PMOS body.
DRC checks out properly
LVS SUCCESS
More LVS success
After a few ever-so-slight modifications and about 3 minutes more of working on it (I read further down on the requirements)
LVS Success
After adding the vdd pin it LVS'd with the original schematic
Now we make our full circuit with the inverter, nand and xor gates.
Make sure the Vpulses are set with these parameters
A:
B:
The ADE L settings are as follows
Our simulation should follow these results.
Now we make the schematic for the full adder
Make the symbol for it
Set up the schematic using the symbol for simulation
Run the simulation,and it should appear as follows (as per the full adder's truth table)
Setting the voltages as such makes the readout cleaner (and allows for the waveforms to follow the appropriate pattern):
Create the layout as follows and DRC it
LVS Success
Set up the ADE environment in the sim to run it with the extracted
Run our sim with the extracted view. Results should be the same as we see below.
Now in ADE we go to menu->simulation->netlist->display to make sure it is indeed the extracted view.
This lab is backed up HERE
Backing up:
As for every lab, all work is backed up using my Dropbox account in an attempt to make sure all is right with the world:
