Next we will create a new cell called inverter.
Lab 5 - ECE 421L
Prelab:
Extract the contents of Tutorial 2 to a folder. In this case I am using lab5.
Next we will create a new cell called inverter.
I opened the schematic for NMOS 4 as well.
Then we hit c and copy the NMOS symbol to the new window.
We do the same for the PMOS and drag it above the NMOS symbol.
Next place gnd and vdd into the schematic as follows
Add input pin A and output pin Ai and wire up the circuit as in the following
After saving cellview as symbol delete all that is in it but for the pins and draw out the shape as follows.
Next prepare up the layouts for NMOS and PMOS in order to lay them out properly in the inverter layout.
Add nmos pmos ntap ptap and m1_poly. To get 2 contacts hit q and adjust columns in properties.
Now everything we need is in this layout.
Line them up all nice.
Wire them up with metal1 and poly layers as follows.
Design is DRC clean. Now save it.
And the extracted view
Create pins with the appropriate names AND input output directions.
The extracted layout is as follows
To my fellow student reading this: Know that if you get this nasty error you either didn't check and save all schematics or you tried to LVS the layout instead of extracted.
LVS SUCCESS
more LVS SUCCESS
Make a new schematic sim_inverter_dc. The noconn is literally in a
library called basic. Add it and wire it up accordingly. Add the names
in and out as follows. ADD vdd as well.
In the ADE L set up stimulus with the parameters as follows.
The rest of the simulation settings are as follows.
Then the transfer curve is as follows.
Set up the environment for simulating the extracted view.
Run the extracted simulation.
From the netlist display we have
Lab Report:
First copy the directory to a new directory and prepare the library to accommodate the larger sizes of PMOS and NMOS devices
The NMOS layout now has been resized to 24u by 600n by virtue of a multiplier of 4 and DRCd.
The NMOS extracted view is as follows
The NMOS schematic is updated with the new parameters.
Update the NMOS symbol accordingly.
Now we do the PMOS the same way. The layout is as follows with DRC results.
The extracted view is as follows
We do the same thing in the PMOS for the schematic but the width is now 48u but with a 4x multiplier.
We now update the symbol and make sure the labels reflect the new parameters for the PMOS
For the new inverter layout we instantiate the ntap and ptaps with 2 rows and 8 columns as such
Instantiate the m1_poly with 1 row and 3 columns as well.
The ntaps and ptaps should look like this:
The ntap, ptap and m1_poly should look like this:
The initial layout should appear as follows:
After wiring it up with metal1 and poly and arranging all of the
elements it ahould appear as follows. DRC it and there should be no
errors.
Our extracted view appears as the following:
LVS Success!
More LVS Success!!!
Now we go back to the smaller sizes (I did it backwards, and wanted to
get the more difficult one out of the way). Instantiate n and p-taps
with these settings.
The initial layout will look like this.
The finished layout will appear as follows:
LVS Success!
More LVS Success!!!!
Now let's update the symbols we created earlier with the appropriate labels:
Add the dc voltage pulse to the circuit with these settings:
Instantiate the inverter for the first circuit (12u PMOS and 6u NMOS
with lengths of 600nm). Give the capacitor value a name that can be used
as a variable (I used 'CP').
Set up simulation as follows. NOTE To save time, you can add the
capacitor under variables edit in the ADE L window and then change the
parameters as needed for each simulation.
Remember to include ami06N and p .m files, otherwise you will get some nasty errors and no pop-up simulation window.
The first transient response with the 100f capacitor is as follows:
The second transient response with the 1pf capacitor. As the capacitance
gets larger, the delay in the output increases. The output also appears
smoother:
With the 10pF capacitor, the output drastically changes and it appears it is approaching a flat line as compared to the input.
With the 100pf capacitor, the output is almost flat at top voltage with much less fluctuation in the signal.
Now we create the exact same circuit as before but with the 48u PMOS and 24u NMOS.
Now we run the sim for the second circuit at a capacitance of 100f. The output looks similar to the first 100f simulation.
Again, there is less fluctuation in the output - similar to the previous
circuit (Unless there is something I should check, all of these look
pretty much the same from here through to the last sim).
With the 10pf capacitor, it is very similar to the previous circuit with the same capacitance.
With the 100p capacitor, again, the results line up similarly to the previous circuit.
Now we will set Ultrasim by going to the ADE L menu and selecting setup, simulator directory host and selecting Ultrasim.
Remember to set up model libraries as before - otherwise you will get some rather annoying errors.
Our first sim with the cap at 100f appears as follows. Other than a
slightly smoother response, the output appears similarly to the previous
sims using 100fF.
Similarly, with the 1p the response looks similar to the one in spectre in both circuits.
Again, as in the previous circuit and simulator, there is less fluctutaion - a flattening of the output signal.
As with the previous sims this response (with 100pF) is very flat.
Now we run Ultrasim in the larger inverter (48u and 24u). The response with the 100fF looks the same as the others using this capacitance.
There is the slight flattening of the response with the 1pF, and it appears smoother (unless my eyes are fooling me) as well using Ultrasim.
Other than a slightly smoother output (it seems), the sim using the 10pF appears similar to all others using this capacitance.
Alas - we get to the final sim. Using the 100pF capacitor, the result
appears smooth, and flattened like the other simulations using this cap
value.
The zip file for this lab can be found HERE
Backing up:
As for every lab, all work is backed up using my Dropbox account in an attempt to minimize the effects of Murphy's Law:
