Lab 4 - ECE 421L
Prelab:
The first thing we do is create a new cell view schematic and call it NMOS_IV_3:
We then select the NMOS from NCSU_Analog_Parts
Next, we add in/out pins:
After creating the symbol I deleted all pins and re-drew shape, adding text for width and length:
I then created the circuit and placed symbol in it:
From this point, navigate to $HOME/ncsu-cdk-1.6.0.beta/models/spectre/standalone and select ami06N.m (to get the NMOS):
Next, select VGS and add value 0:
We then will set up ADE and configure it as follows:
After setting up ADE L, go to menu->tools->parametric analysis and set up with SWEEP1 LINEAR. Variable is VGS from 0 to 5 and STEPSIZE of 1 and run the parametric analysis:
Next, create a new layout, add rectangles, metal 1 layers, poly and
m1_poly (NOTE: You draw the metal 1 layer over the top m1_poly square
before adding poly layer!), then DRC the layout:
After that, we have a new completed layout with pins and labels (DRC'd without errors):
The extracted view is as follows:
After changing pins, we have the layout as:
At this point, run the simulation with pins changed to 4 (nmos 4):
Run LVS and there should be no errors:
Next, set up ADE L sim entering 'extracted' before schematic:
We then simulate this:
To make sure the simulation is actually for extracted instead of the schematic, check the netlist:
Now we move to PMOS. Create PMOS_IV schematic as in the photo below, and check save making sure there are no errors:
Next, create the symbol from this PMOS schematic:
Next, as before, create the layout and DRC it to make sure there are no errors:
Our extracted PMOS looks like the following:
Next, create the schematic as below.
Next, set up the simulation as before and run result for PMOS.
*NOTE: If you're a fellow student reading this, you're again in luck:
In the schematic in the tutorial, the instructions were to type in /V0 - however in my schematic, my V0 was swapped with V1.
After repeating many of the above steps after the simulation did not
work and prematurely losing a bit of hair as a result of much wasted
time, I realized this and typed in /V1 instead of /V0. It then worked as
expected.
Simulation:
Finally, the simulation (set up as before, with "extracted" placed before schematic in the environment settings):
Lab
Report: Generate 4 schematics for measuring current vs voltage sweeps
and layouts with 6u/600n NMOS, and 12u/600nm PMOS utilizing probe pads:
Create the NMOS schematic for varying VGS from 0 to 5 V in 1v steps and VDS from 0 to 5 V in1 mV steps.
Set up DC simulation for VGS varying from 0 to 5v in 1V steps
We then set up VGS as a parameter in variables and set an arbitrary value. After this, we go to tools parametric analysis and set as follows:
We set up the parametric analysis such that the variable VGS goes from 0 to 5 in 1 step.
The simulation results are as follows:
Next we make the schematic for the NMOS device with VDS at 100mV and VGS varying from 0 to 2 V in 1 mV steps.
Then we set up the ADE L to simulate such that VDS is 100 mV and VGS varies. (See Parametric analysis as well).
Then we set up the parametric analysis so that VGS varies from 0 to 2 V in 1 mV steps
Then we run the analysis. This took a while until I figured out that I can just run a normal one as only one voltage varies.
We then get ID vs VGS
Now we set up for the simulation.
Parametric Settings:
The simulation results are as follows:
Next we design the schematic for ID vs VSG:
We set up the DC sim as such
The simulation is as follows
Next we lay out a 6u by 600nm NMOS and DRC the layout
We then make our schematic with the probe pads for LVS verification.
We make the layout. Then place the probes and route via the metal 3 layer after metal1, m2_m1 vias, metal2, and m3_m2 vias:
So, coming out of the pins on the NMOS: You have Metal 1 with m2_m1 vias
to Metal2 with m3_m2 vias to Metal 3, which is then extended to the
borders of the pads/probes.
MAKE SURE NOT TO ATTACH THIS TO THE PIN ITSELF OF THE PAD/PROBE!!!
The layout zoomed out is as follows
We then LVS the extracted versus the schematic and verify that it matches
Let us now make a layout for the PMOS with the width at 12u and the length at 600nm.
Now
we make a layout with the 12u by 600n PMOS and place it among the probes
making sure to place the metal layers appropriately for the correct
connection.
So,
coming out of the pins on the PMOS: You have Metal 1 with m2_m1 vias to
Metal2 with m3_m2 vias to Metal 3, which is then extended to the
borders of the pads/probes.
MAKE SURE NOT TO ATTACH THIS TO THE PIN ITSELF OF THE PAD/PROBE!!!
From this point, make the schematic for the PMOS with the probes attached.
Extract the layout so we can LVS layout versus the schematic.
Here is the screenshot of the layout zoomed out
LVS success!!!
The ZIP file for this lab can be found HERE
Backing up:
As for every lab, all work is backed up using my Dropbox account in an attempt to minimize the effects of Murphy's Law:
