Lab 7 - EE 421L 

Authored by Steven Leung

Leungs@unlv.nevada.edu

10/20/2015    

 

 

Pre-lab work

 
 

 Introduction:

         

        The main purpose of this lab is to use busses and arrays to design multiple bit logical elements. In addition, we will be designing afaster speed adder compared to the one designed in lab 6.

  

 Below shows the schematic and simulation for a 4 bit inverter with different loads. Note that I<3:0> means that the one shown symbol represents 4 different instances of that symbol. This same thing applies to the thicker wires.

 

 

 

 

We can see that as the load capacitiance increases, the rise/fall time along with the delay time increases because it will take longer to charge a bigger capacitor. 

 

Below are a series of pictures showing the schematics and symbols for an 8 bit input output NAND, AND, NOR, OR, and inverter gates. Note that for each of the gates shown below, we first start off by drawing the schematic for a single gate, put that into a symbol, make an array of that symbol, and finally make another symbol on top of everything else that represnts the 8 bit logic gate. 

 

 

 

1) NAND


Schematic

Array and bus connection
symbol for 8 bit NAND gate

 

 

 

2)AND


Schematic

Array and Bus Connection
Symbol for 8 bit AND Gate
 
 
 
 3)NOR

Schematic

Array and Bus Connection
Symbol for 8 bit NOR Gate

 

 

4) OR


Schematic

Array and Bus Connection
8 bit OR Symbol

 

 

 

5) Inverter


Schematic

Array and Bus Connection
8 bit Inverter

 

 

Simulation of Gates
 

 To simulate the operation of these gates, I made to pulsing voltage sources cycle through all possible combinations of input to each gate (00 01 10 11) and then used 2 outputs for each gate (noconn and 500fF).

 


Schematic

Output of noconn connection
Output of C = 500fF

 

The idea of arrays and busses can also be applied to more complicated circuit blocks. For example the next part of the lab is to show that the same concepts can be applied to a MUX. 

  

 

 Below is the schematic and simulation of a single bit 2 to 1 MUX


Schematic for 2 to 1 MUX
Simulation of 2 to 1 MUX

Simulation results of MUX

 

 Below is the schematic and simulation for an 8 bit 2 to 1 MUX. This means that there can be 8 bits of A,B, and Z. Note that for the simulation, only 2 of the 8 bits of the MUX were tested to save time and prevent the cirucit from getting messy. 


Array and Bus connection for 8 bit 2 to 1 MUX
Simulation of an 8 bit 2 to 1 MUX

Simulation Results
 
 
 The next part of this lab is to layout an 8 bit full adder. To do this, the first step is to draw the schematic for a 1 bit full adder and simulate it.
 
 
Below are a few pictures showing the schematic and simulation of a 1 bit full adder along with the layout and LVS.
 
 

Full adder schematic
Full adder symbol

Simulation of 1 bit full adder

Layout of 1 bit full adder

Extracted view

LVS match
   
 
After laying out the 1 bit full adder, we can now move on to the 8 bit full adder using the same technique as before (arrays and busses). Below is the schematic and layout of the 8 bit full adder.
 
 

Schematic of 8 bit full adder

Layout of 8 bit full adder

Extracted View

LVS match

  

 

Below is the simulation of one of the cases of the 8 bit full adder. In this simulation, one of the inputs will be all 1's and the other input will be all 0's. The carry in will be a 1. Therefore the expected sum after all the gate delays through the ripple carry adder (after 5ns)  will be carry out =1 ; sn= 0000_0000.

 

 


Simulation schematic

Simulation plot

 

 link to design files are here


Add a return to the listing of your labs