Lab 4 - ECE 421L 

Authored by Steven Leung

leungs@unlv.nevada.edu

Today's date 9/23/15

Pre-lab work

• Back-up all of your work from the lab and the course.  
• Read through this lab before starting it.
  
• Go through Tutorial 2 seen here. 
• In the simulations in this lab the body of all NMOS devices (the substrate) should be at ground (gnd!) and the body of all PMOS devices (the n-well) should be at a vdd! of 5V.  

Lab description

The first part of this lab is to plot IV characteristic curves for NMOS and PMOS device. The NMOS device will be 6u/600n and the PMOS device will be 12u/600n.

 Below shows the ID v. VDS (SD) and ID v. VGS (VSG) curves for NMOS and PMOS devices and the schematic to achieve this. 

ID versus VSD	ID versus VSD (VGS stepping from 0 to 5 V)
ID versus VGS	ID versus VGS
ID versus VSD	ID versus VSD (VSG sweeping from 0 to 5 V)
ID versus VSG	ID versus VSG

.Pad Schematic

Pad Symbol

Pad layout

Schematic	Symbol
Full Layout	Layout zoomed in	Extracted
DRC pass with no errors	LVS pass (netlist match)

 Below is the layout for the PMOS device

Schematic	Symbol
Full view layout	Zoomed in layout	Extracted
DRC pass with no errors	LVS Pass (netlist match)

Design files are here

Clock here to the listing of your labs