Lab 3 - ECE 421L 

Authored by Steven Leung

leungs@unlv.nevada.edu

9/14/15

   

 

Prelab work

Lab description

         

        The main purpose of this lab is to layout the DAC designed in lab 2. We will then compare a few simulations from a schematic versus layout of the DAC. 

 

     The first step to layout a DAC is to start at the very bottom. This means that we will first layout a 10K n-well resistor. From MOSIS, the sheet resistance is about 800 ohms/square. I choose the width of the n-well to be 4.5 and using the equation 10k=800 * (L/W). We can calculate the length of the n-well to be 57.  Although these L and W do not produce exactly 10k, we needed Ls and Ws to be divisible by the grid (which is .15). 

 

    To measure the width and length of the resistor we can use a ruler. The bind key for a ruler is k. 

 

Below are two pictures showing the value of the n-well resistor and measuring the W and L using a ruler. 

 

                     Extracted view shoing value of n-well resistor

 

 

                                                                                                                Measure the W and L of the n-well resistor via ruler

 

 

Below are a few pictures showing the layout, DRC, and LVS of a single bit of the DAC. Instead of layout out 3 10k n-well resistors for a single bit again, we can call the resistor we layed out above as an instance.

  

 

Layout of a single bitDRC with no errorsLVS (netlist match)
 
 
Calling this single bit of the DAC as an instance, the next step is to layout a 10 bit DAC (call 10 bit instances).
Below are a few pictures showing the layout, DRC, and LVS of the 10 bit DAC.
 
 
Layout of 10 bit DACNo DRC Errors
LVS pass (netlist match)

 

In order to sim the layout of the DAC, we will have to obtain an extracted view (this is also done before performing the LVS check). After this we can launch ADEL got to setup -> environment and then add the word "extracted" before schematic on the first line. This will tell the simulator to simulate the extracted view (layout) instead of the schematic. 

  

Below are a few simulations showing the difference between the schematic simulation and extracted layout simulation. 

 

 

Schematic simulation of DACLayout simulation of DAC
   
 
 
Schematic simulation of 10k loadLayout simulation of 10k load
 
NOTE: The schematic simulation of the 10k load sim is only to 500ns becuase the simulation is having convergence problems. We can force it to converge by changing the options in the simulation options (simulation -> options -> analog). From looking at the plots from t=0 to 50ns, we can see that the two plots are very similar if not exactly the same.
 
Schematic simulation of a 10k and 10pF loadLayout simulation of a 10k and 10pF load
 
NOTE: The same convergence problems are occuring here for the schematic simulation.
 
Schematic simulation of delay on MSBLayout simulation of delay on MSB

 
 
Conclusion
        From the 4 plots comparing the schematic and layout simulations seen above, the result is as exptected. The layout simulation closely replicate the schematic simulations. The schematic view's purpose of Cadence is to provide  a mean for quick simulation. Once we see that our design works (as in lab 2) we can then do the layout and proceed to get the chip fabricated (part of lab 3). 

 Here is a link to design and simulation files in cadence. 


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