Lab #8: MOSIS_chip4 

Authored by:

Brian Kieatiwong, kieatiwo@unlv.nevada.edu

Cassandra Williams, willi131@unlv.nevada.edu

Mari Gilligan  mgill19@unlv.nevada.edu

Russ Prado, prador@unlv.nevada.edu

11/30/2015

  

Generating a Test Chip Layout for submission to MOSIS for Fabrication


In this lab we are putting together a test chip that will be submitted for MOSIS fabrication.

The following structures will be included within this test chip:

MOSIS_Chip4 Test Instructions:

The simulations for each of these devices can be found at Lab Project

MOSIS_Chip4 Padframe:
http://cmosedu.com/jbaker/courses/ee421L/f15/students/kieatiwo/Lab8/images/Padframe.jpg

http://cmosedu.com/jbaker/courses/ee421L/f15/students/kieatiwo/Lab8/images/Schematic.JPG
http://cmosedu.com/jbaker/courses/ee421L/f15/students/kieatiwo/Lab8/images/Layout.JPGhttp://cmosedu.com/jbaker/courses/ee421L/f15/students/kieatiwo/Lab8/images/DRC.JPG
 
http://cmosedu.com/jbaker/courses/ee421L/f15/students/kieatiwo/Lab8/images/1.JPG
The image above shows how Lab 8 work is to be zipped and emailed to myself for backup.
 
To download the cells from this lab, click here

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