Lab 5 - ECE 421L 

Authored by Jared Hayes 

hayesj18@unlv.nevada.edu 

October 5, 2015

Lab Description:
    Design, layout and simulation of a 12u_6u inverter and a 48u_24u inverter.

Create a schematic of a 12u_6u inverter with minimum lengths of 600n using PMOS_IV (12u width) and NMOS_IV (6u width) instances.  Tie the body of the PMOS to VDD and body of the NMOS to ground.

Create a schematic of a 48u_24u inverter by changing the multiplier parameter in the properties of the NMOS and PMOS.

Create symbols for both

Layout 12u_6u

Layout the inverter by instantiating a PMOS, NMOS, ntap and ptap.  Set the taps to be 4 columns long to cover the width of the inverter.

Place vdd!, gnd!, A and Ai pins on the metal1 layer.  The A pin goes on the gate between the transistors and the output goes to the source/drain of the transistors.

 Power (vdd!) is connected to the n-well using the ntap cell.

Ground (gnd!) is connected to the p-substrate using the ptap cell.

Verify the layout is correct by running DRC and LVS.

Layout 48u_24u

Like in the schematic, change the properties of the nmos and pmos devices to have a multiplier of 4.  Follow the same steps as with the above layout.

Verify the layout is correct by running DRC and LVS.

Simulations

Create individual schematics for simulating the inverters.  Have them drive 100 fF, 1 pF, 10 pF, and 100 pF capacitive loads.

Use the Ultrasim simulator to simulate and repoint to the MOSFET models.  Useful for larger circuits at the cost of accuracy.

100fF

1pF

10pF

100pF

Backup:

Cadence files and lab report are automatically backed up in my Dropbox folder.
  

 
The cadence files can be found here: lab5_jh.zip
 
 
 

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