Lab 5 - EE 421L Fall 2015

Design, layout, and simulation of a CMOS inverter. 

 

Mario De La Torre

delatm2@unlv.nevada.edu

10/05/2015 

Zip folder containing Lab5 files found here.

  Pre-lab

 Back-up all of your work from the lab and the course.
 
Go through Tutorial 3 seen here.

 

The purpose of this tutorial is to draw the schematic, symbol, and layout of a CMOS inverter. And also simulate the DC behavior of the inverter.

 

 1. Here is the draft of the inverter using an NMOS of 6u/600n and a PMOS of 12u/600u, and 2 pins A and Ai.  Also after the schematic was completed a symbol was created.

 

http://cmosedu.com/jbaker/courses/ee421L/f15/students/delatm2/Lab5/pre1_schem_sym.JPG

 

2. Layout view for the inveter and DCR.

  

http://cmosedu.com/jbaker/courses/ee421L/f15/students/delatm2/Lab5/pre1_layout.JPG

 

3.  Extracted  view.

 

http://cmosedu.com/jbaker/courses/ee421L/f15/students/delatm2/Lab5/pre1_extracted.JPG

 

4. LVS with no errors.

  

http://cmosedu.com/jbaker/courses/ee421L/f15/students/delatm2/Lab5/pre1_LVS.JPG

  

5. Simulation using the schematic.
 
http://cmosedu.com/jbaker/courses/ee421L/f15/students/delatm2/Lab5/pre1_sim_dc.JPG
 
6. Simulation using the extracted view.

 

http://cmosedu.com/jbaker/courses/ee421L/f15/students/delatm2/Lab5/pre1_sim_dc_extracted.JPG

  

This concludes Tutorial 3.


Post-Lab

 

1. The 12u/6u Inverter.

 

    a. Schematic view.

  

http://cmosedu.com/jbaker/courses/ee421L/f15/students/delatm2/Lab5/post1_inverter_12u_6u_schem.JPG

 

    b. Symbol view.

 

http://cmosedu.com/jbaker/courses/ee421L/f15/students/delatm2/Lab5/post1_inverter_12u_6u_schem_sym.JPG

 

    c. Layout and DRC.

 

http://cmosedu.com/jbaker/courses/ee421L/f15/students/delatm2/Lab5/post1_inverter_12u_6u_layout_DRC.JPG

  

    e. Extracted view.

 

http://cmosedu.com/jbaker/courses/ee421L/f15/students/delatm2/Lab5/post1_inverter_12u_6u_extracted.JPG

    d. LVS with no errors.

    

http://cmosedu.com/jbaker/courses/ee421L/f15/students/delatm2/Lab5/post1_inverter_12u_6u_LVS1.JPG

   

http://cmosedu.com/jbaker/courses/ee421L/f15/students/delatm2/Lab5/post1_inverter_12u_6u_LVS2.JPG

 

Simulations of the 12u/6u inverter using spectre.

 

    a. Capacitve load 100f f. Because of the small capacitance the output and input are almost identical.

     

http://cmosedu.com/jbaker/courses/ee421L/f15/students/delatm2/Lab5/post1_inverter_12u_6u_sim_100f.JPG

 

    b. Capacitve load 1p f.  As the capacitance increases the output gets distorted. It takes more time to charge and disccharge the capacitor.

http://cmosedu.com/jbaker/courses/ee421L/f15/students/delatm2/Lab5/post1_inverter_12u_6u_sim_1p.JPG   

 

    c. Capacitve load 10p f. The capacitor is too big not enough time to discharge and charge properly.

  

http://cmosedu.com/jbaker/courses/ee421L/f15/students/delatm2/Lab5/post1_inverter_12u_6u_sim_10p.JPG

 

     d. Capacitve load 100p f.  The capacitor is too big not enough time to discharge.

 

http://cmosedu.com/jbaker/courses/ee421L/f15/students/delatm2/Lab5/post1_inverter_12u_6u_sim_100p.JPG

 

Simulations of the 12u/6u inverter using ultrasim.

 

    a. Capacitve load 100f f. This simulator is much faster than spectre but less accurate, we can see this effect on the output's peak.

      

http://cmosedu.com/jbaker/courses/ee421L/f15/students/delatm2/Lab5/post1_inverter_12u_6u_sim_100f_ultrasim.JPG

 

    b. Capacitve load 1p f.

http://cmosedu.com/jbaker/courses/ee421L/f15/students/delatm2/Lab5/post1_inverter_12u_6u_sim_1p_ultrasim.JPG

   

    c. Capacitve load 10p f.

 

http://cmosedu.com/jbaker/courses/ee421L/f15/students/delatm2/Lab5/post1_inverter_12u_6u_sim_10p_ultrasim.JPG

  

     d. Capacitve load 100p f.

  

http://cmosedu.com/jbaker/courses/ee421L/f15/students/delatm2/Lab5/post1_inverter_12u_6u_sim_100p_ultrasim.JPG

 



1. The 48u/12u Inverter.

 

    a. Schematic and symbol view.

  

http://cmosedu.com/jbaker/courses/ee421L/f15/students/delatm2/Lab5/post2_inverter_48u_24u_schem_sym.JPG

    

    b. Extracted view. 

 

http://cmosedu.com/jbaker/courses/ee421L/f15/students/delatm2/Lab5/post2_inverter_48u_24u_extracted.JPG

 

    c. Layout and DRC.

 

http://cmosedu.com/jbaker/courses/ee421L/f15/students/delatm2/Lab5/post2_inverter_48u_24u_layout_DRC.JPG

  

    d. LVS with no errors.

 

http://cmosedu.com/jbaker/courses/ee421L/f15/students/delatm2/Lab5/post2_inverter_48u_24u_LVS1.JPG

 

http://cmosedu.com/jbaker/courses/ee421L/f15/students/delatm2/Lab5/post2_inverter_48u_24u_LVS2.JPG

 

Simulations of the 48u/12u inverter using spectre.

 

    a. Capacitve load 100f f. Because of the small capacitance the output and input are almost identical.

     

http://cmosedu.com/jbaker/courses/ee421L/f15/students/delatm2/Lab5/post2_inverter_48u_24u_sim100f.JPG

 

    b. Capacitve load 1p f. Because of the small capacitance the output and input are almost identical.

 

http://cmosedu.com/jbaker/courses/ee421L/f15/students/delatm2/Lab5/post2_inverter_48u_24u_sim1p.JPG 

 

    c. Capacitve load 10p f. As the capacitance increases the output gets distorted. It takes more time to charge and disccharge the capacitor.

  

http://cmosedu.com/jbaker/courses/ee421L/f15/students/delatm2/Lab5/post2_inverter_48u_24u_sim10p.JPG

 

     d. Capacitve load 100p f. The capacitor is too big not enough time to discharge and charge properly.

 

http://cmosedu.com/jbaker/courses/ee421L/f15/students/delatm2/Lab5/post2_inverter_48u_24u_sim100p.JPG

 

Simulations of the 48u/12u inverter using ultrasim.

 

    a. Capacitve load 100f f. This simulator is much faster than spectre but less accurate, we can see this effect on the output's peak.

      

http://cmosedu.com/jbaker/courses/ee421L/f15/students/delatm2/Lab5/post2_inverter_48u_24u_sim100f_ultrasim.JPG

 

    b. Capacitve load 1p f.  This one the output is not as square as the spectre's simulation.

   

http://cmosedu.com/jbaker/courses/ee421L/f15/students/delatm2/Lab5/post2_inverter_48u_24u_sim1p_ultrasim.JPG

 

    c. Capacitve load 10p f.

 

http://cmosedu.com/jbaker/courses/ee421L/f15/students/delatm2/Lab5/post2_inverter_48u_24u_sim10p_ultrasim.JPG

 

     d. Capacitve load 100p f.

 

http://cmosedu.com/jbaker/courses/ee421L/f15/students/delatm2/Lab5/post2_inverter_48u_24u_sim100p_ultrasim.JPG

 

Backing up my work.

1. A zip folder will be created Lab2.

   

http://cmosedu.com/jbaker/courses/ee421L/f15/students/delatm2/Lab5/zip_lab5.JPG

   

2. Then the zipped folder will be store on my google drive.

  

http://cmosedu.com/jbaker/courses/ee421L/f15/students/delatm2/Lab5/google_lab5.JPG

 

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