Lab 6 - ECE 421L 

Degracia, Manuel C.

degracia@unlv.nevada.edu

19 October 2015 

  

Pre-Lab


Post-Lab
   
Objectives:
 
Process:
 
2-Input NAND Gate:
By following the steps in Tutorial #4, one can create the 2-Input NAND Gate displayed below.
 
Schematic:

http://cmosedu.com/jbaker/courses/ee421L/f15/students/degracia/Lab6/Photos/1.%20Nand2%20Schematic.JPG

   

Symbol:

http://cmosedu.com/jbaker/courses/ee421L/f15/students/degracia/Lab6/Photos/2.%20Nand2%20Symbol.JPG

     

Layout:

http://cmosedu.com/jbaker/courses/ee421L/f15/students/degracia/Lab6/Photos/5.%20Nand2%20Layout.JPG

     

http://cmosedu.com/jbaker/courses/ee421L/f15/students/degracia/Lab6/Photos/15.%20Nand2%20DRC.JPG

   

Extracted View/LVS:

http://cmosedu.com/jbaker/courses/ee421L/f15/students/degracia/Lab6/Photos/6.%20Nand2%20LVS%20Extracted%20Layout.JPG

   

http://cmosedu.com/jbaker/courses/ee421L/f15/students/degracia/Lab6/Photos/7.%20LVS%20Match.JPG

    

Output:  

http://cmosedu.com/jbaker/courses/ee421L/f15/students/degracia/Lab6/Photos/8.%20LVS%20Output.JPG

   

2-Input XOR Gate:

Following the same steps and concept of the NAND Gate explained in Tutorial #4, create the schematic below for the XOR Gate. Be sure that all the MOSFETS sizes are the approriate length and width for this may cause errors later in the process.    

   

Schematic:

http://cmosedu.com/jbaker/courses/ee421L/f15/students/degracia/Lab6/Photos/9.%20Xor2%20Schematic.JPG

   

Symbol:

http://cmosedu.com/jbaker/courses/ee421L/f15/students/degracia/Lab6/Photos/10.%20Xor2%20Symbol.JPG

      

Layout:

Using the schematic as reference, create the following layout. In order to not have paths crossing each other (such as poly and metal1 layers connecting at intersections where they shouldn't), use metal2 and m2_m1/m1_poly combinations to get the needed connections. DRC and LVS.

 

http://cmosedu.com/jbaker/courses/ee421L/f15/students/degracia/Lab6/Photos/11.%20Xor2%20Layout.JPG

          

http://cmosedu.com/jbaker/courses/ee421L/f15/students/degracia/Lab6/Photos/14.%20Xor2%20DRC.JPG

       

Extracted:  

http://cmosedu.com/jbaker/courses/ee421L/f15/students/degracia/Lab6/Photos/12.%20Xor2%20Extracted%20and%20LVS.JPG

       

Output:

http://cmosedu.com/jbaker/courses/ee421L/f15/students/degracia/Lab6/Photos/13.%20Xor2%20LVS%20Output.JPG

        

Simulation of Inverter, XOR, NAND

To test the validity of the created gates, we can create a simulation cell.

      

Schematic:

http://cmosedu.com/jbaker/courses/ee421L/f15/students/degracia/Lab6/Photos/17.%20Schematic%20All.JPG

        

Use the following voltage parameters for the inputs (variation permitted).
   

http://cmosedu.com/jbaker/courses/ee421L/f15/students/degracia/Lab6/Photos/20.%20Voltage%20%231%20Parameters.JPG  http://cmosedu.com/jbaker/courses/ee421L/f15/students/degracia/Lab6/Photos/21.%20Voltage%20%232%20Parameters.JPG

   

Analysis:

http://cmosedu.com/jbaker/courses/ee421L/f15/students/degracia/Lab6/Photos/16.%20Tran%20All.JPG

      

Truth Tables:
   

http://cmosedu.com/jbaker/courses/ee421L/f15/students/degracia/Lab6/Photos/18.%20Xor%20Truth%20Table.JPG    http://cmosedu.com/jbaker/courses/ee421L/f15/students/degracia/Lab6/Photos/19.%20Nand%20Truth%20Table.JPG

  

Comparing the truth tables and transient response, one can see that the created gates work properly. Noise found in the transient response can be due to rise and fall times found in the pulse. One can reduce this noise by varying the rise/fall times.

   

Full-Adder:
Lastly, we combine the NAND and XOR Gates to create a Full-Adder.
   
Schematic:

http://cmosedu.com/jbaker/courses/ee421L/f15/students/degracia/Lab6/Photos/22.%20Full%20Adder%20Schematic.JPG

      

Symbol:

http://cmosedu.com/jbaker/courses/ee421L/f15/students/degracia/Lab6/Photos/23.%20Full%20Adder%20Symbol.JPG

      

Layout:
The layout is very tedious and strenuous; thus, be sure to constantly DRC to verify the design is following appropriate parameters.
 

http://cmosedu.com/jbaker/courses/ee421L/f15/students/degracia/Lab6/Photos/25.%20Full%20Adder%20Layout.JPG

   

http://cmosedu.com/jbaker/courses/ee421L/f15/students/degracia/Lab6/Photos/24.%20Full%20Adder%20DRC.JPG

   

Extracted:

http://cmosedu.com/jbaker/courses/ee421L/f15/students/degracia/Lab6/Photos/26.%20Full%20Adder%20Extracted.JPG

      

http://cmosedu.com/jbaker/courses/ee421L/f15/students/degracia/Lab6/Photos/24.%20LVS.JPG

    

http://cmosedu.com/jbaker/courses/ee421L/f15/students/degracia/Lab6/Photos/25.%20LVS%20Output.JPG

 

Simulation Schematic:

http://cmosedu.com/jbaker/courses/ee421L/f15/students/degracia/Lab6/Photos/26.%20Full%20Adder%20Sim%20Schematic.JPG

   

Unfortunately, I couldn't get my Full-Adder to simulate; therefore, I won't be able to show a simulation of my design. That is the only error I had in my lab. I most likely have issues with my pulse voltages.
 

Back up files

Afterwards, it is always important to backup files by either creating a folder on your personal computer, emailing the files to yourself and/or backing it up on a cloud (dropbox, icloud, google drive).

    

http://cmosedu.com/jbaker/courses/ee421L/f15/students/degracia/Lab6/Photos/Back%20up.JPG

    

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