EE
421L - Final Project
Generating a Test Chip Layout for Submission to MOSIS for
Fabrication
Project
Fabricated
using the C5
process through MOSIS.
First
half of the project (no layout, just schematics and
symbols), of your design and an html report detailing
operation (including simulations), is due at the beginning of lab on
Nov. 9.
Ensure
that you have schematics with simulations for all of the cells listed
below.
Your
up/down counter, for example, should be simulated showing, counting up,
down, or both, resetting then counting, etc.
Put
your report (proj.htm) in a folder called /proj in your
directory at CMOSedu.
Dr.
Baker will go over your designs with you, including running
simulations, when lab meets on Nov. 9.
Second
half of the project, a verified layout and documention (in
html), is due at the beginning of lab on
Nov. 23.
Again,
I will meet with you on Nov. 23 to go over your layout and, again, put
your report in the /proj folder in your directory at CMOSedu.
Ensure
that there is a link on your project report webpage to your zipped
design directory.
Finishing
the projects by Nov. 23 will give us time to assemble chips for
fabrication through MOSIS.
- Design of an 8-bit resettable (input "clear")
up/down counter
- The outputs of your counter should be buffered before
connecting to a pad
- A 31-stage ring oscillator with a buffer for driving a 20
pF off-chip load
- NAND and NOR gates using 6/0.6 NMOSs and PMOSs
- An inverter made with a 6/0.6 NMOS and a 12/0.6 PMOS
- Transistors, both PMOS and NMOS, measuring 6u/0.6u where
all 4 terminals of each device are connected to bond pads (7 pads +
common gnd pad)
- Note that only one pad is need for the common gnd pad.
This pad is used to ground the p-substrate and provide ground to each
test circuit
- Using the 25k resistor laid out below and a 10k resistor
implement a voltage divider (need only 1 more pad above the ones used
for the 25k resistor)
- A 25k resistor implemented using the n-well (connect
between 2 pads but we also need a common gnd pad)
Resistor Voltage Divider
Transistors
NAND and NOR Gates
31 Stage Ring Oscillator
Buffer used to drive the 20pF load. |
31 Stage Ring Oscillator with Output Buffer.
Test Schematic
|
8 Bit Loadable,
Asynchronous Clear/Set, Up Down Counter
Above is the simulation of the D flip flop properly latching and
operating with the asynchronous clear/set.
Counter
1bit Counter Cell:
8 bit Counter
Schematic used to simulate the 8bit Counter
Starting from a clear, counting all the way up from 0 to 255.
Starting
from a clear, counting all the way down from 0 to 0 (wrap around from
first 0 to 255)
Loading input of 01010101 and then counting up and switching to
counting down.
Enable, and asynchronous clear and set test.
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