Lab 7 - ECE 421L
See the EE421L webpage here
Authored by Juan Buendia
buendiaj@unlv.nevada.edu
November 1, 2015
Objective: To learn how to use buses and arrays when designing word inverters, multiplexers, and high speed adders
Create
a four word inverter using a bus (wide wire). The four word
inverter is simply four inputs in parallel fed into four corresponding
inverters which give four inverted outputs.
Boolean expression (for i =0,1,2,3)
A<i> = A<i>'
Truth Table
A<0>
is modeled driving no capacitive load which means the delay is ONLY due
to the Resistances and Capacitances of the NMOS and PMOS devices of its
corresponding inverter. A<1>' , A<2>', and
A<3>' devices are modeled driving a 1pF, 500fF, and 100fF.
The capacitive loads will affect the delays in A<1>' , A<2>', and A<3>' in addition to the Resistances and Capacitances of the NMOS and PMOS devices of their corresponding inverter.
Since
I used 6u/0.6u NMOS and PMOS devices, the delays from high to low and
low to high will be different with the delay from low to high longer.
Had this been a 12u/6u inverter the delay from low to high and the delay from high to low would have been equal.
Create a schematic for an eight input/output AND gate:
Each input/output of the array AND Gate will have the following boolean expression and truth table
Boolean expression
O = AB
Truth Table
Create a schematic for an eight input/output array NAND gate:
Each input/output of the array NAND gate will have the following boolean expression and truth table
Boolean expression
O = (AB)'= A' + B'
Truth Table
Create a schematic for an eight input/output OR gate:
Each input/output of the array OR Gate will have the following boolean expression and truth table
Boolean expression
O = A + B
Truth Table
Create a schematic for an eight input/output array NOR gate:
Each input/output of the array NOR Gate will have the following boolean expression and truth table
Boolean expression
O = (A + B)'=A'B'
Truth Table
Create a schematic for an eight input/output array Inverter:
Each input/output of the array Inverter will have the following boolean expression and truth table
Boolean expression
A= A'
Truth Table
Create and simulate the schematic for a 2:1 mux/demux
0 = AS+BS'
Create an 8-bit wide word 2-to-1 DEMUX/MUX schematic and symbol.
Include an inverter in your design so the cell only needs one select
input, S (the complement, Si, is generated using an inverter).
Use simulations to verify the operation of your design.
This is simply four 2-to-1 DEMUX/MUXes
Create a schematic, symbol, and layout of an AND-OR-Inver(AOI) logic Adder
Boolean expression
S = Cin'B'A+Cin'BA'+CinA'B'+CinAB
Cout= AB+BCin+ACin=AB+Cin(A+B)
Cout'=(AB+Cin(A+B))'=(A'+B')(Cin'+A'B')
If we let Cout'(A+B+Cin)=(A'+B')(Cin'+A'B')(A+B+Cin)
(A'Cin'+A'B'+Cin'B'+A'B')(A+B+Cin)
(Cin'A'+A'B'+Cin'B')(A+B+Cin)
Cin'BA'+CinA'B'+CinB'A
We can rewrite S with the following boolean expression
S=Cout'(A+B+Cin)+ABCin
Truth Table
| Cin | B | A | (Cout)' | Cout | S |
| 0 | 0 | 0 | 1 | 0 | 0 |
| 0 | 0 | 1 | 1 | 0 | 1 |
| 0 | 1 | 0 | 1 | 0 | 1 |
| 0 | 1 | 1 | 0 | 1 | 0 |
| 1 | 0 | 0 | 1 | 0 | 1 |
| 1 | 0 | 1 | 0 | 1 | 0 |
| 1 | 1 | 0 | 0 | 1 | 0 |
| 1 | 1 | 1 | 0 | 1 | 1 |
AOI Full Adder Schematic
AOI Full Adder Symbol
AOI Simulation Schematic
AOI Full Adder simulation resutls
I backed up my files by zipping my lab 7 folder and emailing it to myself.
