Lab 6 - ECE 421L
See the EE421L webpage here

Authored by Juan Buendia
buendiaj@unlv.nevada.edu
October 18, 2015

Objective: To design, layout, and simulate a NAND gate, XOR Gate, and a Full Adder.

NAND GATE
In digital electronics, a Nand Gate, is an electrical device that takes two inputs, and outputs the logical high (1) if any one of the inputs is a logic low (0), and (ofcourse) if both inputs are logic high (1's) then it outputs a logic low (0).

Boolean expression
O = (AB)' = A' + B'

Truth Table

B	A'	O
0	0	1
0	1	1
1	0	1
1	1	0

NAND Gate

Schematic	Layout	Extracted	Symbol

Error Check
DRC	LVS

NAND GATE
In digital electronics, an XOR Gate is an electrical device that takes two inputs (in this case), and outputs the logical high (1) if the inputs are complements of each other (when one input is low the other is high).

Boolean expression
O = AB' + A'B 

Truth Table

B	A'	O
0	0	0
0	1	1
1	0	1
1	1	0

XOR Gate
Schematic	Layout	Extracted	Symbol

Error Check
DRC	LVS

NAND, XOR, and Inverter Simulations
DRC	LVS

FULL ADDER
In digital electronics, a full adder is an electrical device that takes three inputs (such as A, B, and Cin for a carry in), and outputs the boolean sum of all three (i.e 1+1 = 10, 1+0=0)
Boolean expression
S = Cin'(A'B+AB')+Cin(AB)
Cout= AB+BC+AC

Truth Table

Cin	B	A	Cout	S
0	0	0	0	0
0	0	1	0	1
0	1	0	0	1
0	1	1	1	0
1	0	0	0	1
1	0	1	1	0
1	1	0	1	0
1	1	1	1	1

Schematic



Layout



Extracted

Symbol




DRC



LVS



Simulation Schematic



Simulation Regular Results



Simultion Results from Extracted




I zipped the file and emailed it to myself as a backup



Return to buendiaj's labs
Return to EE421L Labs