Lab 5 - ECE 421L
See the EE421L webpage here
Authored by Juan Buendia
buendiaj@unlv.nevada.edu
October 4, 2015
Objective: To design, layout, and simulate of a CMOS inverter
In
digital electronics, an inverter (often called a NOT Gate), is an
electrical device that takes an input and negates itm(outputs the
logical opposite of the input)
Boolean expression
A = A'
Truth Table
- Draft schematics, layouts, and symbols for two inverters having sizes of:
- 12u/6u (= width of the PMOS / width of the NMOS with both devices having minimum lengths of 0.6u)
- 48u/24u where the devices use a multiplier, M = 4
Schematics
| 12u/6u | 48u/24u (notice the m=4) |
 |  |
| Layouts |
| 12u/6u | 48u/24u |
 |  |
| Symbols |
| 12u/6u | 48u/24u |
 |  |
| DRC |
| 12u/6u | 48u/24u |
 |  |
| LVS |
| 12u/6u |
 |
| 48u/24u |
 |
- Using SPICE simulate the operation of both of your inverters showing each driving a 100 fF, 1 pF, 10 pF, and 100 pF capacitive load
- Comment, in your report, on the results
The simulations were set up as parametric analyses using spice.
| Simulation Schematics |
| 12u/6u | 48u/24u |
 |  |
| Simulation Results |
| 12u/6u | 48u/24u |
 |  |
lab5.zip
Return to buendiaj's labs
Return to EE421L Labs