Lab 6 - EE 421L 
Authored by Youssef Abdallah,
abdaly1@unlv.nevada.edu
October 19, 2015
   
Pre-Lab

• Back-up all of your work from the lab and the course.
• Go through Cadence Tutorial 4 seen here.
• Read through the lab in its entirety before starting to work on it

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 Lab Report
 
 Part 1:

•  The schematic, symbol and layout of a 2-input NAND gate using 6u/0.6u MOSFETs (both NMOS and PMOS)

 
 
 
   
 

• No DRC errors and the LVS shows that Netlists match

 
    

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 Part 2:  

•  The schematic, symbol and layout of a 2-input XOR gate using 6u/0.6u MOSFETs (both NMOS and PMOS)

 
   
 
     
 

• No DRC errors and the LVS shows that Netlists match

 
     

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•  Simulation of the logical operation of the gates for all 4 possible inputs (00, 01, 10, and 11) 

 

 

 

• At t = 200ns, The output gives a false result. This is due to the timing of the input pulses; because A and B are changing at the same time, it causes glitches in the output of the gate.

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Part 3:  

•  The schematic, symbol and layout of a Full Adder using XOR and NAND gates

 
   
 
     
 

• No DRC errors and the LVS shows that Netlists match

 
    
 
 

•  Simulation of the logical operation of the Full Adder for all 8 possible inputs

 

 

• The lab6 design directory could be downloaded from the following link lab6.zip

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 All the work has been saved and backed up to Google Drive
 

  
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