Lab 7 - ECE 421L 

Ting Yu,

Email: yut2@unlv.nevada.edu

October 25, 2014

Lab description: using buses and arrays in the design of word inerter, muxes, and high-speed adders.

Prelab:

Go through Tutorial 5 from here

Main lab: 

4-bit Inverter

Create a new schematic for 4-bit inverter and instansiate a 1-bit inverter. It should look like the following. 

Create a symbol.

Simulate the symbol by adding 3 capacitor load to the output. Should look the following.

Simulation result. Set the run time to 50s. Capacitive load incluce the delay and rise/fall time, delay time gets longer as the capacitor increase.

Schematic and Symbol for the following:

NAND 

NOR 

AND

Inverter

OR

8-Bit input/output array

8 bit NAND schematic and symbol

Do the same for 8 bit NOR, AND, Inverter and OR

8 bit AND, NOR, AND, Inverter, and OR schematic and symbol Simulation schematic and result

Simulation schematic and result

2-1 mux schematic and symbol

Simulation schematic and result

de-mux schematic and symbol

Simulation schematic and result

8-bit full-adder

Simulation result

Schematic

layout of 8-bit full adder

DRC and LVS for no error

Lastly, back up all the files of Lab7