Lab 6 - ECE 421L 

Ting Yu,

Email: yut2@unlv.nevada.edu

October 17, 2014

Lab description: Design, layout, and simulation of a CMOS NAND gate, XOR gate, and Full-Adder.

Prelab:

Go through Tutorial 4 from here

Create a new schematic for NAND gate. Lay it out with pmos and nmos. It should look like the following.

Create a new symbol

Open the layout view. To get rid of the pins in the middle of the nmos. Select the first and second nmos. Go to edit->hierarchy->flatten. Unselect preserve pins geometries. Select flatten pcells, and flatten vias. Delete the vias and metal 1 in the middle. The new layout should look like the following. 

DRC and LVS for no error

Simulate the NAND gate. Create a new schematic. 

Start ADE-L. Go to setup->model to include the following models

Set Analog Stimuli for Global sources

Set the source parameter as the following

Set Analyses to tran and let it run for 100ns

Press run. You should get the following result.

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Main lab:

• Draft the schematics of a 2-input NAND gate (Fig. 12.1), and a 2-input XOR gate (Fig. 12.18) using 6u/0.6u MOSFETs (both NMOS and PMOS)
• Schematic of 2-input NAND gate
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• Schematic of 2-input XOR gate
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• NAND and XOR symbol
• NAND layout, DRC and LVS for no error
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• XOR layout, DRC and LVS for no error 
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• Use Spectre to simulate the logical operation of the gates for all 4 possible inputs (00,01,10,11)
• Schematic should look like this
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• Simulation results
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• Full Adder Schmatics
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• Full Adder Symbol
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• Simluation results of Full Adder
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• Simulation result should match the following table

  a	b	cin		s	cout
  0	0	0		0	0
  0	0	1		1	0
  0	1	0		1	0
  0	1	1		0	1
  1	0	0		1	0
  1	0	1		0	1
  1	1	0		0	1
  1	1	1		1	1

      

• Layout the Full Adder by placing the 5 gates end-to-end so that vdd! and gnd! are routed
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• DRC and LVS for no error
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Lastly, back up all the files of Lab6