Lab 5 - ECE 421L 

Ting Yu,

Email: yut2@unlv.nevada.edu

October 12, 2014

Lab description: Design, layout, and simulation of a CMOS inverter. We will design inverters using PMOS and NMOS transistor. Schematic, symbol and layout will be created for a 12u/6u and a 48u/24u inverter.  Simulation will be run driving different capacitive loads: 100 fF, 1 pF, 10 pF, and 100 pF.

Prelab: 

Back up all works.

Go through Tutorial 3 from here.

Create -> New Cell for a 12u/6u inverter. Lay down 4 terminal NMOS and PMOS Like the following. Connect wire and put label to each part.

Then create symbol view. Delete everything except the red dot. Then draw lines and circles. 

Now create layout view. Look like the following.

DRC and LVS for errors.

Now repeat the steps for a 48u/24u inverter by copying the 12u/6u inverter and make changes. 

Schematic should look like the following.

Then create symbol view and the layout view like the following

DRC and LVS for no errors.

Now open up the 12u/6u schematic and add component like the following.

Launch ADE-L. Go to Setup include Model and select the following.

Simulation should look like the following

Next, in the ADE, select Setup -> Stimuli and the parameters seen below.

Hit OK and run  simulation.

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Main Lab:

• In this lab we drafted the schematics, layouts, and symbols for two inverters having sizes of: 
• 12u/6u (= width of the PMOS / width of the NMOS with both devices having minimum lengths of 0.6u)
• 48u/24u where the devices use a multiplier, M = 4 (set along with the width and length of the MOSFET), as seen below

SPICE simulation of 12u/6u:

100 fF

1 pF

10 pF

100 pF

Conclusion: As the capacitor value increase the delay for the inverted input to propagate to the output increase. Therefore, inverter have a limitation on what capacitance it can drive. 

SPICE simulation of 48u/24u:

100 fF

1 pF

10 pF

100 pF

Conclusion: As the capacitor value increase the delay for the inverted input to propagate to the output increase. Therefore, inverter have a limitation on what capacitance it can drive. The 48u/24u inverter with 4 multiplier set in the parameter in PMOS and NMOS allow the transistor to handle driving larger capaciance better. It improve the performance of inverter by reducing the time delay. 

UltraSim simulation of 12u/6u:

  
1 pF

 
10 pF

 
100 pF 

UltraSim simulation of 48u/24u:

100 fF

  
1 pF

 
10 pF

 
100 pF 

Conclusion: the result of both Ultrasim simulation is very similar to the SPICE simulation.

Lastly, back up all the files of lab5.