Lab 4 - ECE 421L
Prelab:
Create a new schematic cell called NMOS_IV_3.
press i and select NCSU_ANalog_Parts -> N_Transistors -> nmos.
set MOSFET width to 6u and length to 600nm
Now add pins with direction inputOutput as seem below
We will not create a new symbol as in tutorial 2.
Create a new layout for NMOS_IV_3.
Next go to Create -> Cell View -> From Cell View. Use NCSU_TechLib_ami06 libarary and select nmos.
Set width to 6um. And press e to change display option to level stop to 10 and select pin names.
Now you should have nmos layout like the below.
Add m1_poly cell and a poly rectangle to connect gate. Add metal1 over taps on the two sides like below.
Now add pins to the nmos. Create -> pin
Save. DRC for no errors.
Now repeat the process for NMOS with 4 pins. Create a new schematic NMOS_IV_4. Look like the below. Connect the 4th pin to gnd!
instantiante a ptap cell for gnd!
DRC and LVS for no errors.
Now repeat for PMOS3
Layout should look like this:
Copy PMOS3 to PMOS4. Change the schematic to look like this.
Layout should look like this:
DRC and LVS for no errors.
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NMOS
Create I-V cruves. First create a new schematic call sim_NMOS_IV. Set NMOS width to 6 um and length to 600nm.
Check and save. Lanuch ADE-L.
Go to Setup -> Model Libraries.
Include the models ncsu-cdk-1.6.0.beta->models->spectre->standalone. Select ami06N.m and ami06P.m.
Go to Variables->edit. Add VGS with initial value 0.
Choose the Analysis method like the below
The ADE window should look like this
Now go to Tools->Parametric Analysis. Set the parameters as below. Then hit the green button.
The following simulation graph should appear.
Now repeat for NMOS4. Copy files in sim_NMOS_IV to sim_NMOS4. Open the schematic and replace nmos with nmos4. Keep width at 6um and length at 600nm.
It should look like the following:
The ADE window should look like this
Hit run and the simulation should look like this:
PMOS
Repeat the process for the PMOS. Copy sim_NMOS_IV to sim_PMOS3. Open the schematic.
Change VGS to VSG. Add another voltage source and set it to 5V.
Name the wire on top as vdd!. Change the nmos to pmos and set width to 12um and length to 600nm.
Launch ADE-L and load state. Change VGS to VSG. Run parametric analysis.
Simulation should look like the following
Now copy the file in sim_PMOS to sim_PMOS4. Open and change the schematic and it should look like the following:
Launch ADE-L. We will be plotting ID v. VSG with VSD = 100 mV and vary VSG from 0 to 2 V in 1 mV steps..
Simulation should look like this:
Lay out a 6u/0.6u NMOS device and connect all 4 MOSFET terminals to probe pads (which can be considerably smaller than bond pads [see MOSIS design rules] and directly adjacent to the MOSFET (so the layout is relative small).
DRC and LVS for no errors
DRC and LVS for no errors
