Lab project - ECE 421L
Authored
by Worku, Yetneberk
Email: workuy@unlv.nevada.edu
NHSE ID 1007208058
11/10/2014
introduction:
The
purpose of this project is to make 8-bit Arithmetic Logic Unit (ALU),
that will implement on cedence; there are different ways to design of
the ALU, however on this project we have the most logic gate schematice
privous lab. so, this project the arithmetic and logic unit (ALU) is a
combinational citcuit that performs logic and aritmatic operations; the
operations performed by an ALU are controlled by a set of
function-select inputs and depending
on the value of the control lines, the output will be addition,
subtraction, AND, and OR of the inputs.
F(1) and F(0) as the controls for deciding which function to perform see the following table
to
perform substractor A-B will it takes the two's compliment of B
that perform this [A+(-B)], and B useing 1 for the carry-in. for adding
use A+B.
The ALU symbol, i use see the image below.
the schematically, here is what i want to bulid, see the image below.
Next,
need to check the alu perform the right output, that is done by doing
some simulations. i will start with addition A+B simulations,
which is my input F0=1, and F1=0. for instance if value of A is 11000010, and the value of B is 01110011. the result i am
expecting is 00110101. see the schematic and the simulations reslt
below.
Next, substraction operations [A+(-B)] simulations, which is my input F0=1, and F1=1. for
instance if value of A input is 11100010, and the value of B input is 01000001, then complement of B is 10111110.
the result i am expecting is 10100001. see the schematic and the
simulations reslt below.
http://cmosedu.com/jbaker/courses/ee421L/f14/students/workuy/lab7/lab7.zip
Next,
logic operatins AND simulations, which is my input F0=0, and F1=0. for
instance if value of A input is 11100010, and the value of B input is
01000001. then according to the truth table; the result i am expecting
is 01000000. see the schematic and the
simulations reslt below.
Next, logic operatins OR simulations, which is my input F0=1, and
F1=1. for
instance if value of A is 11100010, and the value of B is 01000001.
then according to the truth table; the result i am expecting is 11100011. see the schematic and the
simulations reslt below.
http://cmosedu.com/jbaker/courses/ee421L/f14/students/workuy/lab7/lab7.zip
concludes,
for the first part of project is both the or and and operatins
cout still output a value carry out shoud be ignored
Part Two (II) project
On
this part, we need to create a layout for 8 bit ALU. however, to
accomplish this task need to create one bit ALU then connect each other
up to 8 bit. for one bit ALU see below the schematic, extracted and
layout, also see the result for DRC and LVS.
next,
using one bit alu, then can bulid the 8 bit alu. see below the
schematic, extracted and layout, also see the result of DRC and LVS.
finally, this is the end of ALU.....
backup work see below
the project download is here
Add a return to the listing of your labs
Return to the listing of my labs
Return to the whole class report
Return to the EE421L site
Return to the CMOSedu.com