Lab 07 - ECE 421L 

Authored by Worku, Yetneberk

Email: workuy@unlv.nevada.edu

NHSE ID 1007208058

10/24/2014

Pre-Lab seven

Post-Lab seven

next, create a symbol for the cscematic something like the following

next, using this symbol create a simulation, and schematic. also, all four inverters' inputs are tied together to an input pulse source. then the out<0> is not connected to a load while out<3> is connected to a 100fF load, and more or less that the out<1> is connected to a 1 pF load while out<2> is connected to a 500 fF load. seen the image showing below.

next, seen simulating results in the following image below.

next, create schematics, symbols for 8-bit input and ouput array of NAND, NOR, AND, Inverter, and OR gates.

for 8-bit inverter:

we, have already creat 4-bit inverter, so copy that and edit object properties change the name to IO<7:0>; that creates 8 inverters, so this will have 8 input and outputs, see the image below, aslo see symbol below.

next, we can simulate this function, however see schematic and the simulation result below.

for 8-bit NAND gate

next, completed NAND gate the schematic and symbol are showing below.

next, we can simulate this function, however see schematic and the simulation result below.

for 8-bit AND gate

next, completed AND gate the schematic and symbol are showing below.

next, we can simulate this function, however see schematic and the simulation result below.

for 8-bit OR gate

next, completed OR gate the schematic and symbol are showing below.

next, we can simulate this function, however see schematic and the simulation result below.

for NOR gate

next, completed NOR gate the schematic and symbol are showing below.

next, we can simulate this function, however see schematic and the simulation result below.

next, create the 8-bit mux and demux component

first, create a one bit mux, so see the completed schematic and symbol below.

next, we can make 8-bit mux, so see complated schematic and symbol below.

next, time make simulation, see the schematic and result image below.

observation, B is outputted when S is low, and A is outputted when S is high.

next, doing demux just convert the mux int  a demux by  changing output to input, and input to output. see the complated schematic and sumulation result below.

8-bit Full Adder:

a single bit adder showing below pass drc and lvs

fig_layout_full_adder.JPG

now, create 8-bit full adder, see the complated schematic and symbol of 8-bit full adder the image below

now, create layout for this schematic, see the image of completed layout below. it pass drc, but fail lvs

next, to test 8-bit full addeer functins worku or not, however it work see completed result, the image below.

comment on lab7 we are familer the basic component about adder, that make as learn somting.

backup the lab7 and e-mail it my self

the lab7 download is here

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