Lab 3 - ECE 421L 

Authored by Silvestre Solano,

Email: Solanos3@unlv.nevada.edu

9-29-2014

 

Prelab

For the prelab, I must go through the boredom of  Tutorial 1  again.

 

First, I build the simple resistor divider shown below.

 

http://cmosedu.com/jbaker/courses/ee421L/f14/students/solanos3/lab3/19.JPG

 

Afterwards, it will be simulated to show the input and output as shown below

 

http://cmosedu.com/jbaker/courses/ee421L/f14/students/solanos3/lab3/20.JPG

 

After the succesful run of the simulation, the schematic will have its voltage source removed and have pins added as shown below.

 

http://cmosedu.com/jbaker/courses/ee421L/f14/students/solanos3/lab3/21.JPG

 

A symbol view will be created for the schematic shown above. The symbol is shown below.

 

http://cmosedu.com/jbaker/courses/ee421L/f14/students/solanos3/lab3/22.JPG

 

This new symbol view will be incorporated into the original schematic as shown below.

 

http://cmosedu.com/jbaker/courses/ee421L/f14/students/solanos3/lab3/23.JPG

 

The schematic shown above was also simulate to verify its correctness and the simulation results are identical to the one shown at the beginning (second picture). 

 

 

Postlab

 

 

In order to begin the postlab, Tutorial 1 must be finished with the desing of the 10K resistor. In order to design the 10k resistor, the lenght and width must be determined first. Since the sheet resistance for the n-well is about 800 Ohms/square, the ratio of length and width, L/W, is determined to be at least 25/2. Since the C5 process only allows a minumum width of 3.6u, I scaled the resistor dimensions by multiplying both length and width by 3.6. This led to the new L/W of 90/7.2. After creating the n-well rectangle of the appropriate dimensions the two n-taps and the res_id layer was added. The completed work is shown below.

 

http://cmosedu.com/jbaker/courses/ee421L/f14/students/solanos3/lab3/1.JPG

 

After completing the above steps, the layout was DRC'd with no apparent errors. Then the layout was extracted which resulted in the hilariously wrong resistor value of 16.87k Ohms shown below. 

 

http://cmosedu.com/jbaker/courses/ee421L/f14/students/solanos3/lab3/2.JPG

 

This is due to the resistor length being to big for the single n-tap contacts. I could have just added two more n-taps on each side of the resistor to correct this mistake, However, I thought it would be better to scale the width to match the n-tap width as shown below.

  

http://cmosedu.com/jbaker/courses/ee421L/f14/students/solanos3/lab3/3.JPG

 

Therefore, the original dimensions of 25/2 had to be rescaled by multiplying both lenght and width by 4.5/2, which led to the new and improved L/W of 56.25/4.5. However, this new L/W still wasn't good enough for some reason, at least according to the DRC I did for it, so I changed one last time to 56.4/4.5. The DRC finally let this one pass. The final 10k resistor design is shown below. Interestingly enough, professor Baker used nearly identical values in his tuturial. 

 

http://cmosedu.com/jbaker/courses/ee421L/f14/students/solanos3/lab3/4.JPG

  

To measure the length or width of the resistor, the k keybind must be pressed in order to access the ruler. The ruler can be used to measure stuff such as the length of the resistor as shown below.

 

http://cmosedu.com/jbaker/courses/ee421L/f14/students/solanos3/lab3/24.JPG

 

The extracted view for the 10k resistor gives a reasonable value of 10.26k Ohms and is shown below.

 

http://cmosedu.com/jbaker/courses/ee421L/f14/students/solanos3/lab3/5.JPG

 

In order to create the 10 bit DAC layout, I duplicated the resistor 3 times and connected them with metal 1 as shown below.

 

http://cmosedu.com/jbaker/courses/ee421L/f14/students/solanos3/lab3/7.JPG

 

The layout shown above is supposed to match the layout shown below.

 

http://cmosedu.com/jbaker/courses/ee421L/f14/students/solanos3/lab3/17.JPG

 

After using DRC, which resulted in no errors, I used LVS for the schematic and the extracted view and the results are shown below.

 

http://cmosedu.com/jbaker/courses/ee421L/f14/students/solanos3/lab3/9.JPG
 
 The next step is to duplicate these three resistors 10 times in order to replicate the process in Lab 2. The resistors were connected together by metal 1 wires and the zoomed out view of all ten is shown below.
 
http://cmosedu.com/jbaker/courses/ee421L/f14/students/solanos3/lab3/11.JPG
 
A more detailed view is shown below.
 
http://cmosedu.com/jbaker/courses/ee421L/f14/students/solanos3/lab3/15.JPG
 
The total layout is supposed to match the schematic shown below, in which the "resistor cells" are supposed to contain three resistors each.
 
http://cmosedu.com/jbaker/courses/ee421L/f14/students/solanos3/lab3/16.JPG
 
After using DRC and extracting the layout, the LVS is used and the failed results are shown below.
 
http://cmosedu.com/jbaker/courses/ee421L/f14/students/solanos3/lab3/12.JPG
 
This error was due to me adding the "Top", "Bottom", and "input" pins in the layout, which for some reason, did not match the schematic. Ironically, I added those pins in the layout in order to avoid this error in the first place. This error set me back a couple of hours. After deleting the pins from the layout, the LVS was done again and it finally worked. This is shown below.
 
http://cmosedu.com/jbaker/courses/ee421L/f14/students/solanos3/lab3/13.JPG
 
And this concludes Lab 3, which took a lot longer to finish than it should have.

The final design can be found on this zip file. Please take note that only the folder named "R10Ke" has the complete and final design. The others have previous versions that I copied in case something went horribly wrong.
 

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