Project - ECE 421L 

Authored by Silvestre Solano,

Email: Solanos3@unlv.nevada.edu

11-24-2014

For the lab final project, I will construct a schematic and a layout for a simple 8-bit ALU. ALU stands for "Arithmetic Logic Unit" and it essentially performs addition, subtraction, bitwise OR, and bitwise AND operations.To perform these operations,  the 8-bit versions of the CMOS full adder, AND gate, OR gate, and the 2 to 1 MUX designed in lab 7 will be used. 

The addition, bitwise OR, and bitwise AND operations are easy and straightforward to implement. However, the subtraction operation requires more thought. In order to subtract numbers in the form of A-B, the B bits will have to be represented as a negative number. One way to do this is to use 2's complement numbers. In 2's complement, the leftmost bit, which would be considered the MSB in unsigned binary, is used as the sign bit. A leftmost 0 would indicate a positive number and a leftmost 1 would represent a negative number. In orderto convert an unsigned number into its negative 2's complement representation, the unsigned number must be inverted bitwise and then a LSB 1 must be added. For example, 00000001 represents 1 in unsigned binary and to converted into 2's complement it will be inverted to 11111110, and then 1 will be added to create 11111111, which represents -1 in 2's complement. Adding the unsigned 00000001 and signed 11111111 yields 00000000 (1-1=0) if the carry out is ignored. When adding in 2's complement, the carry out must be ignored. 2's complement gives the correct result unless overflow occurs. Overflow occurs when a number requires more bits than are available. For this ALU, overflow will occur when 9 bits are needed to represent any number. In 2's complement, the maximum range of negative numbers that can be used without overflow follows the equation-[2^(n-1)-1] . For 8 bits, this corresponds to the number -127. To accomplish this in the ALU, a full adder must have its B bits inverted and its carry in, Cin, must be set to a logic 1.

Schematic

The schematic is fairly easy to construct considering the fact that 95% of it was finished in lab 7. My original idea for the ALU was to use the 8-bit AND, OR, inverter, and 2 full adders with 3 cascaded MUX as shown below.

After much thought however, I decided to modify the above ALU so that it would only require the use of one 8-bit full adder. The reason for my modification is that I realized that I would eventually have to layout the above schematic. I REALLY did not want to layout and wire 2 8-bit full adders as my original design indicated. So I changed it to the ALU shown below, which is my final design.

In the above ALU, the "Cout8" carry out is not used. In theory, I could have used it to indicate overflow or to display the 9th bit in an overflow situation, but I decided not to use it because it can be confusing when dealing with 2's complement numbers. As explained before, the carry out in 2's complement addition is ignored in order to display the correct results. So, I thought it would be confusing to display the carry out when it should not be displayed for correct results. Since this ALU design does not use the carry out, it is designed with the assumption that the given 8-bit A and B inputs will not cause an overflow situation. If they do, then the ALU will not display the correct results.

For the 3 MUX, the operation of the F1 and F2 bits are shown in the table below. The top MUX chooses between AND and OR operations and has its selection bit (F2) connected to the selection bit of the bottom MUX. The middle, or rightmost MUX has the selection bit of F1 and chooses between the full adder and the bottom MUX. The bottom MUX inverts the B bits for 2's complement addition (subtraction). The F2 bit feeds into the Cin of the full adder. As seen in the table below, when F2 is 0, addition is choosen and when F2 is 1, subtraction is choosen (assuming F1 is 0 for both cases). Therefore, the selection F2 bit is a 1 for Cin in order for the 2's complement addition (subtraction) to work as explained previously. For addition, the F2 is 0, which works perfectly for addition.

A symbol is created for the above ALU and is shown below.

The simulation circuit is built as shown below. Please note that A<1> represents the LSB and A<8> represents the MSB. Same goes for the B bits.

Simulations

For the first simulation, I will use the numbers A=10010010 (146) and B=00111010 (58). These bits can be seen in the pulse sources of the simulation schematic shown above. The below table shows the expected results from the simulation of the ALU for these bits. The F1 and F2 selection bits are simulated using pulse sources that vary in order to cycle between all possible combinations of F1 and F2 (00, 01, 10, 11). 

The actual results of the simulation are shown below and appear to match the above table. Again, please be aware that Z<8> is the MSB and Z<1> is the LSB.
 

The second simulation involves the following input bits A=01111111 and B=01111111 which are both 127. I choose this number because I stated previously that -127 is the maximum negative number that can be used without causing overflow. The expected results are shown in the table below.

The actual simulation results are shown below.

And last but not least, I will use the input bits of A=01111110 (126) and B=01111111 (127). The reason for choosing these numbers is that their subtraction will create the number -1, which will be displayed in its 2's complement form of 11111111. The table below shows the expected results.

This concludes the schematic and simulation portion of the ALU project.

Layout

To begin the layout, I decided to lay out 8-bit versions of the AND, OR, inverter, and the 2-to-1 MUX. The 8-bit layout of the full adder was already done in Lab 7. Below illustrates the correctly LVS 8-bit AND, OR, inverter, and the 2-to-1 MUX layouts

8-bit AND

8-bit OR

8-bit 2-to-1 MUX

8-bit inverter

Using the above layouts in combination with the previously constructed 8-bit full adder, I will create a layout for the 8-bit ALU. Below shows the needed 8-bit layouts.
 

After spending my entire Saturday afternoon in the TBE-311 Lab, I was able to connect everything together as shown below, with the CWI showing no errors for DRC. Please note that the inputs and outputs of the 8-bit ALU are made with metal3.
 
"The UZI 9mm"

A zoomed in view of the inverters section of the total layout is shown below.
 

 
The OR and AND gates are shown below. They share the same VDD strip (ntap) and the OR gates were flipped vertically and are stacked on top of the AND gates.
 

 
Next, the two MUX who share the same select bit, F2, are shown below in a similar arrangement as the OR and AND gates.
 

 
The 8-bit full adder is shown below with the total layout.
 

 
The connection of the F2 select bit with the 8-bit full adder cin is shown below in better detail. It is connected with metal3.
 

 
The last MUX that has the F1 select bit is shown below, the output bus can be seen to the right. The F1 select connection can be seen in the bottom left hand corner.
 

 
As mentioned before, the inputs (A,B,F1,F2) and the output (Z), are made with metal3 for possible manufacture. They are shown below.
 

 

 

 
The final size measurements are shown below.
 

 
This essentially concludes the 8-bit ALU project.
 
 
 
As always, I will back up my work to my laptop and flash drive as shown below.
 

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