Lab 7 - ECE 421L
The schematic is then simulated and the following picture shows the outputs for each capacitive load.
The above simulation results it easily seen that a bigger capacitance results in a longer required time for discharging/charging. This is due to the time constant RC. For example, the time delay in a RC circuit is defined to be 0.7RC. Since the capacitance is bigger, the 0.7RC equation increases, which increases the delay. This is best shown on the above simulation results in the output "out<1>", which has the biggest capacitave load. In this output, the wave form has more of a "slope" on its rise and file time, which indicate that it takes longer for it to charge/discharge. In contrast, "out<3>" , which has the smallest capacitive laod, has a smaller rise/fall "slope", which indicates that it keep up with the change of the input since it is does not reqire as much time for charging/discharging.
Design and simulation of an 8-bit NOR gate.
For the NOR gate, professor Baker did not provide a schematic to copy. So, I had to google the CMOS schematic for the inverter. I came across the follwing picture. This picture was obtained from the Ohio university and the specific PDF is linked here. It is apparently the work of a person named Basawaraj.
The above schematic was implemented as follows using the 6u/0.6u width and length for all devices.
A symbol was created for the above schematic as shown below.
The OR gate is essentially the same thing as the NOR gate with an inverter attached to its output. Creating the OR gate follows the same procedure as the NOR gate.
The symbol is shown below.
The NAND gate schematic and symbol were taken from lab 6. Again, the AND gate was just the NAND gate with an inverter at its output.
The symbol for the NAND gate.
The AND schematic.
The symbol for the AND gate.
The NOR, OR, NAND, AND, and inverters will have 8 bit versions built and simulated as follows.
8-bit NAND schematic.
Symbol for NAND.
8-bit NOR.
Symbol
8 bit AND
Symbol
8 bit OR
Symbol
8 bit inverter
Symbol
The simulations for the above circuits where made in the single schematic shown below. Since I could not really decide on what the 72 total inputs and the 40 outputs should look like, I just simply input the same signal for A and the same signal for B on all 5 devices. The inputs and outputs follow the simulation schematic shown below.
A and B input for all devices (except the inverter that only accepts one input, A).
Output for AND
Output for NAND
Output for OR
Output for NOR
Output for inverter
This essentially concludes the part of the 8 bit gates. All the gates were named IO<8:1> because I assumed that the 8 meant rows and the 1 meant columns. Also, the above simulations are repeated throught all 8 outputs for each individual device.
Design and simulaiton of a MUX/DEMUX.
For the MUX, professor baker supplied us with the schematic. I simply based the one I created off of his. The schematic for the MUX I designed is shown below. In my design, I made the A, B and Z pins to be inputoutput because they will change from input to output in the DEMUX process.
Its symbol is shown below.
The simulation schematic is shown below. Please take note that the Si input is just the inversion of the S input. Therefore, I put an inverter to automatically take care of the Si input.
The simulation results are shown as follows.
As it can clearly bee seen, the Z output can be the same output as the input A or it can be the same as the input B. It can only be one ore the other. In order to select which one will be choosen, the S input is either 1 or 0. When it is 1, The A input is selected. When the S input is 0, then B is selected.
For DEMUXING, the process is reversed and the Z output becomes the input while A and B become outputs. S selectes whether or not the Z input is transmitted through the A or B outputs. The DEMUX schematic is the same as the MUX, but it is reversed. The schematic for the simulation is shown below followed by the simulation.
The simulaion above seemed right at first until I noticed that B started at a voltage slightly below 4 volts. I believe that this is incorrect, but I spent too much time working on the full adder, so I could not find a solution to this problem. Everything else seems to work fine. However, I believe that B is supposed to start at zero for the above simulation.
8 bit MUX/DEMUX
The schematic and symbol for the DEMUX was changed in order to internally incorporate the inverter for the Si input. The results of this are shown below.
To create the 8 bit mux, the above schematic was used as shown below.
A symbol was created for the 8-bit MUX/DEMUX.
The simulation circuit is as follows.
The simulation results are essentially the same as the single MUX, but with its outputs repeated multiple times.
8-bit CMOS full adder schematic, simulaition, and layout.
The following pictures are used to construct the schematic for the CMOS full adder.
The completed schematic is shown below. In the below schematic, the name "icin" is supposed to be "icout", but I did not change it for fear of having it mess up and starting all over. "icout" stands for the inverted cout.
The symbol for the CMOS full adder is shown below.
The 8 bit CMOS full adder is built using the above schematic. They will be "strung" up together were the cout of the first adder feeds into the cin of the second adder and so on. The first cin, labeled cin1, will be grounded in the simulations. The last cout, labeled cout8, will be treated as an output. The completed schematic is shown below.
The symbol for the 8 bit adder is shown below.
The simulation to test the 8 bit adder is shown below. For the bus input A, I used the test number 10010010 (146) and for the B bus input, I used the test number 00111010 (58). This was done using an individual pulse source for each individual bit. A/B<8> is the MSB and A/B<1> is the LSB. The final schematic is shown below.
The input can be seen in the above schematic, but I also showed them in the following simulation picture. Since there are so many inputs, I will show the output in the picture after the one shown below.
The output is shown below.
The above simulaiton shows an output of 11001100 (204). This is correct because the sum of 146 and 58 is indeed 204. Therefore, I deem this 8 bit adder to be successfull. the s<8> is the MSB and s<1> is the LSB.
Layout of the CMOS 8 bit full adder.
In order to lay out the 8 bit full adder, I will first create the layout for the single full adder and then simply copy and paste the single one 8 times. After hours of work, the completed layout for the single full adder is shown below with the ICW showing no errors for DRC.
The successfull LVS is shown below.
For the 8 bit adder, I copied the one shown above 8 times and connected the cout of the first one into the cin of the second one and so forth. The completed layout is shown below with the CIW showing no errors for the DRC.
And last but not least, the completed layout was LVSed with the 8 bit schematic and ran successfully with matching net lists. This is shown below.
A close up on one of the interconnecting sections of the completed layout is shown below.
This concludes yet another time consuming lab.
As always I will back up my stuff on my laptop and flash drive as shown below.
My lab files used in this lab can be found in this zip.