In this lab we are going to use both the NMOS and the PMOS from the earlier labs to create an inverter. To get familiar with how to do this, we are going to briefly go through Tutorial 3. Once we have completed that for the prelab, we can use some of those things for this lab.
12u/6u Inverter
The first thing we need to do is copy over everything from Tutorial 3. In that tutorial we already created a 12u/6u inverter complete with schematic, layout, extracted view, and symbol. Instead of remaking them, it makes more sense to just copy them over into a new library called lab5 and rename them 12u_6u_inverter.
Once we open up the schematic we need to make sure that the multiplier is set to 1. This will ensure that it stays a 12u/6u inverter.
You can see from the schematic that there are only 2 pins, A for input and Ai for the inverted output. We now need to look at the symbol and make sure it is still correct. We can also add a label to it in order to distinguish it from the inverter we are going to make later.
Now we are going to open the layout and extract it. This will allow us to do an LVS check.
Next step is to go back to the layout and make sure it matches the schematic. First we are going to do a DRC and once that passes we do an LVS. As long as both pass, we can move on to testing out our new inverter.
Now we can go to the cell labeled sim_12u_6u_inverter_dc and modify it to our needs. Here is what it looked like from the tutorial.
We need to change the voltage source connected to the inverter to a pulse source that goes from 0V to 5V with 1ns rise time. We also need to make the voltage source for vdd! by adding a 5V DC source and connecting it to the vdd bus. Finally we need to add a capacitive load to the output of the inverter. We are going to try several different loads (100fF, 1pF, 10pF, and 100pF) to see how they change the output of the inverter. Here is the schematic for the 100fF inverter test.
After a quick check and save we open ADE. Once inside we need to select the simulator as UltraSim. This is a little faster than Spectre while sacrificing some accuracy. UltraSim only allows us to do a transient analysis so we can set it up from 0s to 40ns. We can also select the outputs on the schematic to be A and Ai. Finally, we need to add in the ami06 models for the PMOS and NMOS transistors.
After saving the state for later use we can hit the green arrow and run the simulation. What we should see is for every input we should see its complement in the output i.e. if the input is high, the output is low and vice-versa.
For the other loads all we are going to change is the load. We will be running the exact same simulation. Here is the schematic and plot for the 1pF load.
Here is the schematic and plot for the 10pF load.
Here is the schematic and plot for the 100pF load.
By comparing the plots of the different loads, we can see that by adding loads with more capacitance we are greatly changing the output of the inverter. This is due to the capacitor holding charge and dissipating it when inversion happens. The bigger the capacitor, the more charge it can hold and the larger the effect will be on the output. On the last test circuit, the effect is so great that you almost can't even see the effects of the inverter.
48u/24u Inverter
The 48u/24u inverter is very similiar to the 12u/6u inverter so it makes sense to copy over the cells from 12u_6u_inverter to a new file called 48u_24u_inverter. This way we can make some minor changes and simulate this inverter easily. We can also copy over the sim file since the test circuits will be the same.
Open up the schematic for the inverter and change the multiplier value for the NMOS and PMOS to 4. This will give us the width we need without actually building very large transistors. We will see how this is accomplished later when we modify the layout.
Next we need to change the text on the inverter to match our new values of 48u and 24u. All the other parts of the symbol will be the same.
Open the layout so we can make the layout match the multiplier value of 4 that changed earlier. Select the PMOS and press q to change the properties. Under the parameter tab change the value of the multiplier from 1 to 4. This will add more "fingers" to the PMOS to create the width wanted. Follow the same steps to change the multiplier of the NMOS. Next we want to change the numbers of rows and columns on the vdd! and gnd! contacts. This will make it easier for us to connect the pins of the NOMS and PMOS to them. Make them both 2 rows by 8 columns. To finish the layout we need to connect all the metal and poly parts to their respective areas. Once this is all done, this should be the finished product.
DRC then extract so we can do an LVS.
Once extracted we can do an LVS check.
Now that everything matches, we can simulate the inverter. Since we already copied over the sim file all we need to do is open it and change the inverter in the schematic over to our new 48u/24u inverter. Simulations will be exactly the same as before.
Here is the schematic and plot for the 100fF load.
Here is the schematic and plot for the 1pF load.
Here is the schematic and plot for the 10pF load.
Here is the schematic and plot for the 100pF load.
Just like before we can see that by adding larger capacitive loads we are changing the output of the inverter although with the larger width, the effect is not as noticable. This tells us that with a large enough width, we can negate the effects of the capacitive load.
This concludes Lab 5. As always, I zip up my lab directory and webpage files then backup my files on Google Drive.
Here is a copy of the directory I used in this lab.
