Project - ECE 421L 

Authored by Leanna Guevara, guevaral@unlv.nevada.edu

November 24, 2014 

Design, layout and simulate an 8-bit ALU that can perform A AND B, A OR B, A+B, and A-B.

What is an ALU?

ALU stands for Arithmetic Logic Unit, it is used in the Central Processing Unit (CPU) of computers. The purpose of an ALU is to perform arithmetic and logic operations. For this lab we will be working with and, or, addition and subtraction.

Part 1: Schematics and Symbols (Due: Nov. 10)

For this project we will be using material from previous labs so make sure to copy the files from lab 7 into the project library. It is important to do this step in the beginning to ensure that when the project file is sent, all schematics and symbols can be seen by another user. 

First we need to create the ALU with the symbols already created from previous labs. 

• The logic operations (And and Or) will be straight forward since the symbols have already been created. 
• For the arthmetic operations (Additon and Subtraction) we will sending the inputs through the full adder. Instead of creating a new symbol for the subtractor we can just negate one of the inputs  [A-B=A+(-B)].  
• Multiplexors will be used to chose which function will be displayed in the end

1-Bit ALU

Schematic

 Symbol

   
8-Bit ALU
Schematic
Creating an 8-bit schematic is similar what was done in previous labs (for more information check out Tutorial_5). Notice Cin and Co remains a 1-bit input and out . The Cin and the Couts will be connected through all of the ALUs.

Symbol

   

Based on the schematics the the following outputs should be produced based on F<1:0>

Table

A AND B

Just to see some variation in the schematic, the period for each voltage are different. 

A or B

   
A+B

A-B

End of Part 1

Part 2- Verified Layout (Due: Nov. 24)

1-Bit ALU

Layout

To make trouble shooting easier the layouts for the 1-bit gates were created and LVS in seperate cells. Most of the gate layouts should already be available from previous labs. Since metal2 was used when creating the Full Adder, the inputs were connected on the top and bottom of gates, this will make connecting  the 8-Bit ALU easier. Metal3 could also have been used to connect the inputs safely over the other layers, it was not used in the schematic below since it appeared too messy in early trials. Remember to DRC and save while working to ensure that the layout follows the Cadence rules. 

LVS

Extract the layout and LVS to ensure that layout matches the schematic.

8-Bit ALU

Layout

Insert the 1-bit layout creted earlier eight times and make sure all vdd! and gnd! are connected. Based on the schematic created earlier the Cout needs to be connected to the Cin of the next 1-bit ALU unitl the the last 1-bit ALU is connected.Make sure to DRC and save the layout constantly to ensure that all rules are being followed. Once the 8-Bit layout is created extract the file.

LVS

The results show that the netlist match, therefore the task of the project has been completed!

This the end of the Lab Project. Remember download the library and email for safe keeping. 

Directory for the Project

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