Lab 5 - ECE 421L 

Authored by Leanna Guevara, guevaral@unlv.nevada.edu

October 13, 2014 

  

Design, layout and simulation of a CMOS inverter
   

 For this lab we will be following Tutorial 3 from the Cadence Design System.

    

The first of the lab wants us to draft schematic, layouts and symbols for two inverters. With the following parameters:

  1. 12u/6u (PMOSwidth/NMOSwidth) with the minimum length of 0.6u
  2. 48u/24u with the multiplier M=4
Let's start with the 12u/6u inverters!
    Schematic:
http://cmosedu.com/jbaker/courses/ee421L/f14/students/guevaral/Lab%205/12u6uINVERT.PNG

   

Make sure to check and save the schematic to ensure that there are no errors. To create the symbol go to Create->Cell View-> From Cell View. To create the image below make sure to delete everything except the pins. The inverter symbol is drawn on (Create->Shape->Line). Display the pin names to verify if the pins are in the correct order.

http://cmosedu.com/jbaker/courses/ee421L/f14/students/guevaral/Lab%205/12u6uINV2.JPG

Once you get the proper symbol check and save your work.

Layout:

Add nmos, pmos, ntap, ptap, and m1_ploy to your layout (They can be found in the NCSU_TechLib_ami06 Library)

http://cmosedu.com/jbaker/courses/ee421L/f14/students/guevaral/Lab%205/12u6uINV3.1.JPG

   

Link the cells using metal1 and insert pin names. Note how an extra poly rectangle was added to connect the input A. Make sure to DRC the layout to verify that there are no errors. Check and Save when completed,

http://cmosedu.com/jbaker/courses/ee421L/f14/students/guevaral/Lab%205/12u6uINV3.JPG

When we have the proper layout, extract the file (Verify->Extract). We need the extracted layout to LVS the system.

http://cmosedu.com/jbaker/courses/ee421L/f14/students/guevaral/Lab%205/12u6uINV4.JPG

http://cmosedu.com/jbaker/courses/ee421L/f14/students/guevaral/Lab%205/12u6uINV5.JPG

http://cmosedu.com/jbaker/courses/ee421L/f14/students/guevaral/Lab%205/12u6uINV6.JPG


Before starting the simulations let work on the second inverter. This inverter is 48u/24u and has a multiplier M=4

Layout:

For the second inverter we can copy the same schematic from the first inverter. Pres q (object) to change the multiplier to 4 for both nmos and pmos. We do not change the values for the width and length because the multiplier automatically changes the width to 48u and 24u.

http://cmosedu.com/jbaker/courses/ee421L/f14/students/guevaral/Lab%205/48u24uINV.JPG

   

Symbol:

http://cmosedu.com/jbaker/courses/ee421L/f14/students/guevaral/Lab%205/48u24uINV2.JPG

   

Layout:

To match the schematic we must change the multiplier value for nmos and pmos. Ensure that everything is connected by increasing the size of ntap and ptap.

http://cmosedu.com/jbaker/courses/ee421L/f14/students/guevaral/Lab%205/48u24uINV3.JPG

   

Extracted view:

http://cmosedu.com/jbaker/courses/ee421L/f14/students/guevaral/Lab%205/48u24uINV4.JPG

    

LVS

http://cmosedu.com/jbaker/courses/ee421L/f14/students/guevaral/Lab%205/48u24uINV5.JPG

http://cmosedu.com/jbaker/courses/ee421L/f14/students/guevaral/Lab%205/48u24uINV6.JPG

   

Now that we have both inverters lets run simulations so we can compare differences.
Schematic using the 12u/6u inverter
http://cmosedu.com/jbaker/courses/ee421L/f14/students/guevaral/Lab%205/12u6uINVschematic.JPG
   

Schematic using the 48u/24u inverter

http://cmosedu.com/jbaker/courses/ee421L/f14/students/guevaral/Lab%205/48u24uINVschem.JPG

   

Setting up the simulations:

We will be using the ami06P.m and ami06N.m model libraries (Setup->Model Libraries)

http://cmosedu.com/jbaker/courses/ee421L/f14/students/guevaral/Lab%205/12u6uINV8.JPG

    

For the labs we have been using spectre state as the standard for the simulations, now we will change the simulator value to UltraSim. UltraSim can only be processed using Transient analysis

http://cmosedu.com/jbaker/courses/ee421L/f14/students/guevaral/Lab%205/ultrasim.JPG

   

When C=100f F

http://cmosedu.com/jbaker/courses/ee421L/f14/students/guevaral/Lab%205/12u6uINVgraph1.JPG

http://cmosedu.com/jbaker/courses/ee421L/f14/students/guevaral/Lab%205/48u24uINVgraph1.JPG

   
When C= 1p F
http://cmosedu.com/jbaker/courses/ee421L/f14/students/guevaral/Lab%205/12u6uINVgraph2.JPG
http://cmosedu.com/jbaker/courses/ee421L/f14/students/guevaral/Lab%205/48u24uINVgraph2.JPG
   
When C=10p F
http://cmosedu.com/jbaker/courses/ee421L/f14/students/guevaral/Lab%205/12u6uINVgraph3.JPG
http://cmosedu.com/jbaker/courses/ee421L/f14/students/guevaral/Lab%205/48u24uINVgraph3.JPG
   
When C=100p F
http://cmosedu.com/jbaker/courses/ee421L/f14/students/guevaral/Lab%205/12u6uINVgraph4.JPG
http://cmosedu.com/jbaker/courses/ee421L/f14/students/guevaral/Lab%205/48u24uINVgraph4.JPG
      
After viewing all the simulations we notice for the 12u/6u inverter the fall time increases as the values of the capacitor changes compared to the 48u/24u inverter. Based on the last simulation for the 12u/6u inverter we can assume that the output will be a constant value if we continue to increase the capacitor value
   
If we used the Spectre just like the other labs the simulations (for this graph we used the 12u/6u inverter when C=100f F) would look like
http://cmosedu.com/jbaker/courses/ee421L/f14/students/guevaral/Lab%205/spectre.JPG
We can notice that majority of the graphs looked almost identical. The purpose of UltraSim is to simulate larget schematics.
 

This ends Lab 5

    

Remember to zip and email the file to yourself for safe keeping

http://cmosedu.com/jbaker/courses/ee421L/f14/students/guevaral/Lab%205/zip.JPG

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