EE 421L Lab 7

Authored By Alan Fortes on October 26, 2014

fortesa@unlv.nevada.edu

The lab directory cells are found Lab 7 Directory AF.zip

Part 1: The prelab

 

1st: Be sure to back up all of your work from the course.
 
2nd: Go through tutorial 5. Webpage guide here and video guide here.

 

3rd: Read through the entire lab before starting it.

Part 2: Creating a 4 bit word inverter using a bus line.


Here is the circuit schematic for an inverter. This inverter circuit will be used in the creation of
a 4 bit inverter, using buses.

  
Here is the schematic of a 4 bit inverter, made using the buses. The symbol below is the symbol that corresponds to the circuit seen above.

 
The symbol seen below is the the symbol for the schematic seen above. This symbol will
be used in a testing schematic to prove that the 4 bit inverter works as intended.

 
This schematic is the testing circuit for the 4 bit inverter. There are 4 load types that are connected to the output of the inverter: A simple wire, a 1 picoFarad capcitor, a 500 femtoFarad capacitor, 100 femtoFarad capacitor. 

 
Here is the output of each load, corresponding to the each of the 4 wires of the bus. Capacitive loads influence the rise and fall times of the inverters outputs by slowing the time it takes for the output to rise and fall. Instead having the output of the inverters rise and fall in an abrupt, straight manner, the output is slowed to a gentle slope for rises and falls. The larger the capcitance, the longer it takes for the rise and fall slopes to reach their plateau. The pink curve is the largest capacitance, 1 picoFarad. The orange curve is the 500 femtoFarad capacitor, and the green curve is the 100 femtoFarad capcitor. The 2nd red curve is the output with no capcitance.

 
Part 3: Creating an 8 bit word nand gate using a bus line.
 
Here is the circuit for a nand gate. This will be used in the creation of an 8 bit word gate, using buses.

 
Here is the schematic of the circuit to create an array of 8 nand gates.

 
Here is the symbol of the 8 bit nand gate. 

 
This is the test schematic to ensure that all bits feed through the desired outcome.

  
As it can be clearly seen, the nand gate produces a high output for all bit cases, except for both inputs being high, since it is a nand gate.

 
Part 4: Creating an 8 bit word nor gate using a bus line.
Here is the circuit for a nor gate. This will be used in the creation of an 8 bit word gate, using buses.

 
Here is the schematic of the circuit to create an array of 8 nor gates.

 
Here is the symbol of the 8 bit nor gate.

 
This is the test schematic to ensure that all bits feed through the desired outcome.

  
As it can be clearly seen, the nor gate produces a high output only when the inputs are low.

 
Part 5: Creating an 8 bit word and gate using a bus line. 
 Here is the circuit for making an and gate.

 
Here is the schematic of the 8 bit adder.

 
Here is the symbol for the 8 bit and gate.

 
This is the test circuit for ensuting the and gate produces the appropriate output.

 
As it can be clearly seen, the output turns high when both inputs are high.


Part 6: Creating an 8 bit word inverter using a bus line.
 Here is the schematic for the creating an 8 bit inverter.
 
Here is the symbol for this 8 bit inverter.

  
Here is the schematic using the previously made schematic to test the 8 bit inverter.

 
As you can clearly see, the inverter works, giving the opposite output, of the input.

 
Part 7: Creating an 8 bit word or gate using a bus line.
Here is the circuit necessary to create an or gate.

 
Here is the schematic for creating an 8 bit inverter.

 
Here is the schematic to test the gate to see if all 8 bits produce the adequate output.

  
As it can be seen, all 8 bits show that when at least one of the inputs is high, high output is yielded.

 
Part 8: Creating a 2 to 1 mux and 2 to 1 demux.
 
Part 8A: The 2 to 1 mux
 
Here is a 2 to 1 mux. The way this circuit works, is that when the selection input, S, is high, the output of Z is whatever the signal of A is.
If signal of S is low, the output will be whatever B is. The mechanics of this is that when S is high, the nmos connected the input of A will be allow the current of A to pass through. The input of S is inverted and given to the pmos connected to A. This will allow the current of A to pass through completely. Conversely, the nmos connected to B is given the opposite of S, in this case low, and the pmos of B is given a high input. This prevents the signal of B from passing through. The same principle applies to when S is low, just that the inputs to B's nmos and pmos are switched.

   
Here is the symbol of the mux.

 
Here is the test circuit of the mux, to see if adequate output is given.

 
As you can see, when S is low, the output is what ever the trace of B is, the high frequency input.
When S is high, the output is what A is, the low frequency input.


Part 8B: The 2 to 1 demux

Demux is the reverse of the mux. Instead of selecting from multiple possible inputs, to feed through one output, one input must be chosen to go through one of multiple possible output conduits. The way this works is exactly as the mux, it is just that the inputs of A and B are made outputs, and the output Z, is made into an input.

  
Here is the symbol of the demux.

  
Here is the test schematic for the demux.

 
As you can see, output stream A follows the input pattern, Y, wehen S is high, and output stream B follows the input pattern when S is low. Output stream A is out and output stream B is out2.


Part 9: Creating an 8 bit 2 to 1 mux and 8 bit 2 to 1 demux.

Part 9A: The 8 bit 2 to 1 mux
 
Here is the schematic to make an 8 bit demux.

 
Here is the symbol of the 8 bit mux.

 
Here is the the testing schematic of the 8 bit mux.

 
All 8 bits output the appropriate output, giving the appropriate output for each selection choice.

Part 9B: The 2 to 1 demux
 
Here is the schematic to make an 8 bit demux.

 
Here is the symbol for the 8 bit demux.

 
Here is the test schematic for the 8 bit demux.

 
The chosen output streams match whatever the input is.

 
Part 10: Creating a full adder.
Here is the circuit schematic for a full adder based on figure 12.20.

 
Here is the symbol for a single full adder.

 
In order to ensure that individual adder works, this schematic will test its output.

 
Here, it can be seen that when there is only 1 high input, S goes high. If there are 2 high inputs, cout goes high, and S goes low. If all 3 inputs are high, both S and Cout go high.

 
Part 11: Creating an 8 bit adder.
Here is the schematic for creating an 8 bit adder, using a single schematic, feeding
input into itself using buses.

  
Here is the symbol of this adder.

 
Here is the testing schematic for this adder. Here, we will be adding 01101010 and 10110101 with an external cin coming in.

 
The sum of 01101010 and 10110101 is 100011111. Along with the Cin, the total is 100100000. Our output has only has Cout high, and out<5> high, indicating a correct output.


Part 12: Laying out an 8 bit full adder.
 Here is an individual unit of the soon to be 8 bit adder. The individual unit passes DRC.

 
Here are 8 full adders strung together. This collective unit passes DRC.

 
Here is the extracted version, along with the LVS results. The LVS matches the schematic.

    

Part 13: Backing up this lab

In order to ensure that this lab is not lost forever, I back up my lab by emailing it to myself.