EE 421L Lab 6

Authored By Alan Fortes on October 19, 2014

fortesa@unlv.nevada.edu

The lab directory cells are found lab6_AF.zip

Part 1: The prelab

 

1st: Be sure to back up all of your work from the course.
 
2nd: Go through tutorial 4. Webpage guide here and video guide here.

 

3rd: Read through the entire lab before starting it.

Part 2: Drafting the schematic, layout, and symbol of the nand gate.

 

Here is the draft of the schematic of the 6u by 0.6u two input nand gate. Note the tall cell view, in case more complicated layouts are necessary in the future.

 
Here is an upclose view of this schematic:
 
 
Here is the draft and DRC testing of the layout of the 6u by 0.6u two input nand gate. The layout passes the DRC requirements Note the tall cell view, in case more complicated layouts are necessary in the future.

 
Here is a close up of layout.

 
Here is the extraction and LVS testing of the layout, along with the LVS of the layout being checked against the original schematic. The schematic matches the layout.

 
Finally, here is the symbol of our gate. 


Part 3: Drafting the schematic, layout, and symbol of the xor gate.
 
Here is the draft of the schematic of the 6u by 0.6u two input xor gate. Note the tall cell view, in case more complicated layouts are necessary in the future.

 
Here is an upclose view of this schematic:

 
Here is the draft of the layout of the 6u by 0.6u two input xor gate. The layout passes the DRC requirements Note the tall cell view, in case more complicated layouts are necessary in the future.

 
Here is a close up of layout.

 
Here is the extraction of the layout, along with the LVS of the layout being check against the original schematic. The layout matches the schematic.


Finally, here is the symbol of the xor gate.


Part 4: Simulating input and output of the nand and xor gates.
 
Here is the setup of the schematic to test the output of the two gates that were previously created. All four posibilites of input will be tested for these two input gates.


Here are the outputs of the two gates. They have come out exactly as expected. Since the nand gate is a reverse of the and gate, all combinations of input produce an output of 1, except for an input of 1 for a and 1 for b. The exclusive or gate produces an output of 1 only when a single input is a 1 and the other input is a 0. If both inputs are 1s, or both input are 0s, an output of 0 is output. Whether or not the input pulses of a gate are appropriately timed is a critical factor in the output of a gate. If an input pulse is not appropriately timed, this can cause an erroneous signal to output by feeding the wrong information to the input pin of a gate.


Part 5: Creation and testing of a full adder.

Here is the schematic of a full adder created by using the gates that were previously made.

 
Here is the symbol of this full adder.

   
Here is the circuit using the symbol of the full adder that will simulate output of an input of a sequence of increasing bits.

 
Finally, here is the output of the adder:

 
Here is the layout and DRC testing of the full adder. The layout passes the DRC.

 
Here is a close up of the layout.

   
Here is the extraction and LVS testing of the full adder layout. The layout passes the LVS.


Part 6: Backing up this lab

In order to ensure that this lab is not lost forever, I back up my lab by emailing it to myself.