EE 421L Lab 5

Authored By Alan Fortes on October 11, 2014

fortesa@unlv.nevada.edu

The lab directory cells are found lab5_AF.zip

Part 1: The prelab

 

1st: Be sure to back up all of your work from the course.
 
2nd: Go through tutorial 3. Webpage guide here and video guide here.

Part 2: Drafting schematics of a 12u/6u and a 48u/6u wide

nmos/pmos inverters, both having a length of 0.6u for everything.

 
Here is the draft of the schematic of the 12u/6u by 0.6u PMOS/NMOS. There are 2 pins, A and Ai, represending the input and output of the circuit.
When A is set to ground, the output is set to VDD through the PMOS. If the input is VDD, the ouput is set to ground through the NMOS.

 
Here is the draft of the schematic of the 48u/24u by 0.6u PMOS/NMOS. There are 2 pins, A and Ai, represending the input and output of the circuit.
When A is set to ground, the output is set to VDD through the PMOS. If the input is VDD, the ouput is set to ground through the NMOS.


Part 3: Drafting layouts of a 12u/6u and a 48u/6u wide

nmos/pmos inverters, both having a length of 0.6u for everything.

 

Here is the draft of the layout of the 12u/6u by 0.6u PMOS/NMOS. The layout has 4 pins, vdc!, gnd!, A, and Ai. The DRC verfication shows no errors,

ensuring that all designs rules have been met.


 

Here is the draft of the layout of the 48u/24u by 0.6u PMOS/NMOS. The layout has 4 pins, vdc!, gnd!, A, and Ai. The DRC verfication shows no errors,

ensuring that all designs rules have been met.


 
Here is the extracted version of the 12u/6u by 0.6 PMOS/NMOS inverter. As you can clearly see below, the LVS shows that the extracted layout matches the draft of the schematic.

 
Here is the extracted version of the 48u/24u by 0.6 PMOS/NMOS inverter. As you can clearly see below, the LVS shows that the extracted layout matches the draft of the schematic.

Part 4: Drafting symbols of a 12u/6u and a 48u/6u wide

nmos/pmos inverters, both having a length of 0.6u for everything.


Here is the symbol of the 12u/6u by 0.6 PMOS/NMOS inverter. The symbol has two terminals, A and Ai, one for input and one for output, respectively The symbol now can be used as an instance in a test circuit to obtain simulation results.

 
Here is the symbol of the 48u/24u by 0.6 PMOS/NMOS inverter. The symbol has two terminals, A and Ai, one for input and one for output, respectively The symbol now can be used as an instance in a test circuit to obtain simulation results.

 



Part 5: Running simulations of the 12u/6u driving 100fF, 1pF, 10pF, and 100 pF capcitive loads,
with spectre.

Here are the circuits that will be tested, by driving the aforementioned loads.




Preliminary analysis:
The larger the value of a capacitor, the longer it takes for that device to build up it's voltage.
The same applies to discharging. The larger the capacitance, the longer it takes to discharge.
That means that capacitors with small values should be very quick to reach a fully charged
state. They should also quickly discharge.
Part 5A: Driving a 100fF load
 
Here is the result of a the circuit driving a 100fF load. This rather small capacitance allows the voltage to reach its peak rather quickly; it's almost instant.

Part 5B: Driving a 1pF load

Here is the result of a the circuit driving a 1fF load. This slightly larger capacitance lets the circuit output reach it's peak at about one third of half the period.

Part 5C: Driving a 10pF load

Here is the result of a the circuit driving a 10fF load. This larger capacitance prevents the output from reaching a flatline top, creating a sawtooth pattern. Notice that the output hovers around the middle of square wave. This is probably due to the larger capitance not having fully discharged it's voltage, and having that stored charge ebb and flow, discharging halfway, and then being filled, never completely discharging, and never completely being filled up.

Part 5D: Driving a 100pF load

Here is the result of a the circuit driving a 100fF load. This much larger capitance prevents the initial charge from completely discharging, keeping the output at a high voltage. Since the voltage never discharges from its initial charge, this level of charge is refilled when the square wave reaches zero volts, reaching a max peak of 5 volts. The circuit then discharges the little it can when the square wave reaches 5 volts. This incapability to discharge quickly creates nearly a straight line of output voltage.


Part 6: Running simulations of the 48u/24u driving 100fF, 1pF, 10pF, and 100 pF capcitive loads,
with spectre.

Preliminary analysis:
All of the information regarding capacitors is still applicable in these simulations.
But, since we're dealing with transistors of increased width, more current can
now pass through since, there is a wider avenue of access through the transistor
available, for electrons to pass through. Since this is so, the capacitors should
be able to charge and discharge faster, producing the classic RC (dis)charge
curves, as opposed to saw tooth patterns.

Part 6A: Driving a 100fF load
The 100fF capacitor charges and discharges quickly, as with our 12u/6u inverter.


Part 6B: Driving a 1pF load
The 1pF capacitor now (dis)charges much quicker with the 48u/12u inverter, than with the 12u/6u.


Part 6C: Driving a 10pF load
The 10pF capacitor no longer yields a sawtooth pattern, but charges and discharges, almost completely.


Part 6D: Driving a 100pF load
The 100pF capacitor no longer yields a near straight line, but now gives more of a saw tooth pattern.


Part 7: Running simulations of the 12u/6u driving 100fF, 1pF, 10pF, and 100 pF capcitive loads,
with ultrasim.

Preliminary analysis:
The simulator now being used is ultrasim. This simulator is known for being fast, but inaccurate. It is expected for the output not to be as precise as our previous results.

Part 7A: Driving a 100fF load
With the 100fF load, the difference is negligible.


Part 7B: Driving a 1pF load
With the 1pF load, the rising bulge of the RC (dis)charge curve is no longer as rectangular as is with spectre.

 
Part 7C: Driving a 10pF load
The 10pF ulstrasim's top bulge doesn't protude as much as the spectre simulation. 

 
Part 7D: Driving a 100pF load
With the 100pF load, the difference is negligible.


Part 8: Running simulations of the 48u/24u driving 100fF, 1pF, 10pF, and 100 pF capcitive loads,
with ultrasim.
Part 8A: Driving a 100fF load
Since the circuit is driving 100fF, the difference between it and the 100fF load circuits is negligible.


Part 8B: Driving a 1pF load
The difference between the spectre and ultrasim output is that the ultrasim cuve is not as square as the spectre simulation output.

Part 8C: Driving a 10pF load
This curve is slightly below what the spectre curve is.

Part 8D: Driving a 100pF load
The sawtooth pattern persists, even using ultrasim.


Part 8: Backing up this lab.

In order to ensure that this lab is not lost forever, I back up my lab by sending an email to myself.